Research Article
An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement
Table 2
Brief comparison of the four PDLs.
| | PDL number | 1 | 2 | 3 | 4 |
| | System clock period (ns) | 7.532 | 7.940 | 7.890 | 7.782 | | Clock uncertainty (ns) | 0.087 | 0.035 | 0.035 | 0.087 | | Digital output code | 1650 | 1773 | 1786 | 1726 | | Absolute error | 1 | 1 | 1 | 1 | | Relative error (%) | 1.21 | 0.50 | 0.50 | 1.18 | | Actual delay resolution (ps) | 4.56 | 4.48 | 4.42 | 4.51 | | Nominal delay resolution (ps) | 5 | 5 | 5 | 5 |
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