A Low Leakage Autonomous Data Retention Flip-Flop with Power Gating Technique

<table class="table-group" id="tab1"><tr><td><table class="table"><tr><td class="thead-hr" colspan="3"><hr/></td></tr><tr class="thead"><td align="left">Flip-flops</td><td align="center">Header (um)</td><td align="center">Footer (um)</td></tr><tr><td class="thead-hr" colspan="3"><hr/></td></tr><tr><td align="left">Mutoh-FF</td><td align="center">2.0</td><td align="center">1.0</td></tr><tr><td align="left">Balloon-FF</td><td align="center">/</td><td align="center">1.0</td></tr><tr><td align="left">Memory-TG-FF</td><td align="center">/</td><td align="center">1.5</td></tr><tr><td align="left">ADR-FF</td><td align="center">3.0</td><td align="center">1.5</td></tr><tr class="table-tr"><td colspan="3"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

The sizes of sleep transistors with different data retention flip-flop circuits.

Journal of Electrical and Computer Engineering

tab1

Table 1

Table 1: A Low Leakage Autonomous Data Retention Flip-Flop with Power Gating Technique 