Asynchronous Advanced Encryption Standard Hardware with Random Noise Injection for Improved Side-Channel Attack Resistance

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="837572.fig.0015a" src="https://static.hindawi.com/articles/jece/volume-2014/837572/figures/837572.fig.0015a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>Relative decrease in SNR</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="837572.fig.0015b" src="https://static.hindawi.com/articles/jece/volume-2014/837572/figures/837572.fig.0015b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>Relative increase in difficulty for performing DPA</td></tr></table></td></tr></table>

<table>Comparison of SNR and difficulty of performing successful DPA for both designs.</table>

Journal of Electrical and Computer Engineering

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Figure 15

Figure 15: Asynchronous Advanced Encryption Standard Hardware with Random Noise Injection for Improved Side-Channel Attack Resistance 