Table of Contents Author Guidelines Submit a Manuscript
Journal of Electrical and Computer Engineering
Volume 2015, Article ID 630178, 14 pages
http://dx.doi.org/10.1155/2015/630178
Research Article

Impact of Interface Traps on Direct and Alternating Current in Tunneling Field-Effect Transistors

School of Microelectronics, Xidian University, Xi’an 710071, China

Received 6 May 2015; Revised 5 August 2015; Accepted 12 August 2015

Academic Editor: Muhammad Taher Abuelma’atti

Copyright © 2015 Zhi Jiang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. A. M. Ionescu and H. Riel, “Tunnel field-effect transistors as energy-efficient electronic switches,” Nature, vol. 479, no. 7373, pp. 329–337, 2011. View at Publisher · View at Google Scholar · View at Scopus
  2. E. O. Kane, “Theory of tunneling,” Journal of Applied Physics, vol. 31, no. 1, pp. 83–89, 1961. View at Google Scholar
  3. A. Mallik and A. Chattopadhyay, “Tunnel field-effect transistors for analog/mixed-signal system-on-chip applications,” IEEE Transactions on Electron Devices, vol. 59, no. 4, pp. 888–894, 2012. View at Publisher · View at Google Scholar · View at Scopus
  4. C. Li, Y. Zhuang, and R. Han, “Cylindrical surrounding-gate MOSFETs with electrically induced source/drain extension,” Microelectronics Journal, vol. 42, no. 2, pp. 341–346, 2011. View at Publisher · View at Google Scholar · View at Scopus
  5. C. Li, Y. Zhuang, R. Han, and G. Jin, “Subthreshold behavior models for short-channel junctionless tri-material cylindrical surrounding-gate MOSFET,” Microelectronics Reliability, vol. 54, no. 6-7, pp. 1274–1281, 2014. View at Publisher · View at Google Scholar · View at Scopus
  6. T. S. A. Samuel, N. B. Balamurugan, S. Bhuvaneswari, D. Sharmila, and K. Padmapriya, “Analytical modelling and simulation of single-gate SOI TFET for low-power applications,” International Journal of Electronics, vol. 101, no. 6, pp. 779–788, 2014. View at Publisher · View at Google Scholar · View at Scopus
  7. E.-H. Toh, G. H. Wang, G. Samudra, and Y.-C. Yeo, “Device physics and design of double-gate tunneling field-effect transistor by silicon film thickness optimization,” Applied Physics Letters, vol. 90, no. 26, Article ID 263507, 2007. View at Publisher · View at Google Scholar · View at Scopus
  8. P. Wang, Y. Zhuang, C. Li, Y. Li, and Z. Jiang, “Subthreshold behavior models for nanoscale junctionless double-gate MOSFETs with dual-material gate stack,” Japanese Journal of Applied Physics, vol. 53, no. 8, Article ID 084201, 7 pages, 2014. View at Publisher · View at Google Scholar · View at Scopus
  9. L. Shi, Y. Zhuang, C. Li, and D. Li, “Analytical modeling of the direct tunneling current through high-k gate stacks for long-channel cylindrical surrounding-gate MOSFETs,” Journal of Semiconductors, vol. 35, no. 3, Article ID 034009, 2014. View at Publisher · View at Google Scholar · View at Scopus
  10. A. Chattopadhyay and A. Mallik, “The impact of a high-κ gate dielectric on a p-channel tunnel field-effect transistor,” in 16th International Workshop on Physics of Semiconductor Devices, vol. 8549 of Proceedings of SPIE, p. 5, The International Society for Optical Engineering, Kanpur, India, 2011. View at Publisher · View at Google Scholar
  11. G. B. Beneventi, E. Gnani, A. Gnudi, S. Reggiani, and G. Baccarani, “Can interface traps suppress TFET ambipolarity?” IEEE Electron Device Letters, vol. 34, no. 12, pp. 1557–1559, 2013. View at Publisher · View at Google Scholar · View at Scopus
  12. Y. Qiu, R. Wang, Q. Huang, and R. Huang, “A comparative study on the impacts of interface traps on tunneling FET and MOSFET,” IEEE Transactions on Electron Devices, vol. 61, no. 5, pp. 1284–1291, 2014. View at Publisher · View at Google Scholar · View at Scopus
  13. X. Y. Huang, G. F. Jiao, W. Cao et al., “Effect of interface traps and oxide charge on drain current degradation in tunneling field-effect transistors,” IEEE Electron Device Letters, vol. 31, no. 8, pp. 779–781, 2010. View at Publisher · View at Google Scholar · View at Scopus
  14. M. G. Pala, D. Esseni, and F. Conzatti, “Impact of interface traps on the IV curves of InAs tunnel-FETs and MOSFETs: a full quantum study,” in Proceedings of the IEEE Electron Devices Meeting (IEDM '12), pp. 135–138, December 2012.
  15. S. Hanson, B. Zhai, K. Bernstein et al., “Ultralow-voltage, minimum-energy CMOS,” IBM Journal of Research and Development, vol. 50, no. 4-5, pp. 469–490, 2006. View at Publisher · View at Google Scholar · View at Scopus
  16. TCAD Sentaurus Device Manual, Synopsys, Mountain View, Calif, USA, 2012.
  17. K. Boucart and A. M. Ionescu, “A new definition of threshold voltage in Tunnel FETs,” Solid-State Electronics, vol. 52, no. 9, pp. 1318–1323, 2008. View at Publisher · View at Google Scholar · View at Scopus
  18. B. Laikhtman and E. L. Wolf, “Tunneling time and effective capacitance for single electron tunneling,” Physics Letters A, vol. 139, no. 5-6, pp. 257–260, 1989. View at Publisher · View at Google Scholar · View at Scopus
  19. J. Boehmer, J. Schumann, and H. Eckel, “Effect of the miller-capacitance during switching transients of IGBT and MOSFET,” in Proceedings of the 15th International Power Electronics and Motion Control Conference (EPE/PEMC '12), pp. LS6d.3-1–LS6d.3-5, IEEE, Novi Sad, Serbia, September 2012. View at Publisher · View at Google Scholar
  20. Y. Yang, X. Tong, L.-T. Yang, P.-F. Guo, L. Fan, and Y.-C. Yeo, “Tunneling field-effect transistor: capacitance components and modeling,” IEEE Electron Device Letters, vol. 31, no. 7, pp. 752–754, 2010. View at Publisher · View at Google Scholar · View at Scopus