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Journal of Electrical and Computer Engineering
Volume 2015, Article ID 765485, 13 pages
Research Article

A 3.9 μs Settling-Time Fractional Spread-Spectrum Clock Generator Using a Dual-Charge-Pump Control Technique for Serial-ATA Applications

1Hitachi Central Research Laboratory, 1-280 Higashi-Koigakubo, Kokubunji-shi, Tokyo 185-8601, Japan
2Renesas Electronics Corporation, Tokyo 185-8601, Japan

Received 3 October 2014; Accepted 5 January 2015

Academic Editor: John N. Sahalos

Copyright © 2015 Takashi Kawamoto et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A low-jitter fractional spread-spectrum clock generator (SSCG) utilizing a fast-settling dual-charge-pump (CP) technique is developed for serial-advanced technology attachment (SATA) applications. The dual-CP architecture reduces a design area to 60% by shrinking an effective capacitance of a loop filter. Moreover, the settling-time is reduced by 4 μs to charge a current to the capacitor by only main-CP in initial period in settling-time. The SSCG is fabricated in a 0.13 μm CMOS and achieves settling time of 3.91 μs faster than 8.11 μs of a conventional SSCG. The random jitter and total jitter at 250 cycles at 1.5 GHz are less than 3.2 and 10.7 psrms, respectively. The triangular modulation signal frequency is 31.5 kHz and the modulation deviation is from −5000 ppm to 0 ppm at 1.5 GHz. The EMI reduction is 10.0 dB. The design area and power consumption are 300 × 700 μm and 18 mW, respectively.