Research Article
A 3.9 μs Settling-Time Fractional Spread-Spectrum Clock Generator Using a Dual-Charge-Pump Control Technique for Serial-ATA Applications
Figure 8
Explanation of proposed fast-lock dual-CP SSCG settling operation of the conventional SSCG (a) and the proposed dual-CP controlled technique without VCO high frequency limiter (b) and with limiter (c).