New Current-Mode Integrated Ternary Min/Max Circuits without Constant Independent Current Sources

Table 2

The initial simulation results.

Designs	Delay (psec) TMin	Delay (psec) TMax	Average power (μW)	PDP (fJ)	Static power (μW)	Number of transistors
Previous TMin	19.64	—	72.56	1.42	72.94	19
CSTMin1	14.23	—	46.92	0.66	47.52	16
CSTMin2	11.17	—	43.19	0.48	43.71	18
Previous TMax	—	14.93	75.62	1.12	76.06	19
CSTMax1	—	13.60	56.73	0.77	57.51	21
CSTMax2	—	13.71	50.40	0.69	51.09	23
CITMin/Max1	18.48	20.68	65.06	1.34	65.69	38
CITMin/Max2	18.11	21.38	58.53	1.25	59.06	40
CITMin/Max3	17.57	18.82	54.84	1.03	55.55	30