Applying Partial Power-Gating to Direction-Sliced Network-on-Chip

<table class="figure-group"><tr class="fig-image" id="a"><td><object data="https://static.hindawi.com/articles/jece/volume-2015/862387/figures/862387.fig.009a.svgz" name="862387.fig.009a" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(a) </b>Mesh</td></tr><tr class="fig-image" id="b"><td><object data="https://static.hindawi.com/articles/jece/volume-2015/862387/figures/862387.fig.009b.svgz" name="862387.fig.009b" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(b) </b>Torus</td></tr></table>

<div>Power-consumption comparison in SPLASH simulation.</div>

Journal of Electrical and Computer Engineering

fig9

Figure 9

Figure 9: Applying Partial Power-Gating to Direction-Sliced Network-on-Chip 