Table of Contents Author Guidelines Submit a Manuscript
Journal of Electrical and Computer Engineering
Volume 2015 (2015), Article ID 939028, 10 pages
Research Article

A Formal Verification Methodology for DDD Mode Pacemaker Control Programs

Department of Electrical and Computer Engineering, North Dakota State University, 1411 Centennial Boulevard, Fargo, ND 58102, USA

Received 1 June 2015; Revised 4 August 2015; Accepted 12 August 2015

Academic Editor: Massimo Poncino

Copyright © 2015 Sana Shuja et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Pacemakers are safety-critical devices whose faulty behaviors can cause harm or even death. Often these faulty behaviors are caused due to bugs in programs used for digital control of pacemakers. We present a formal verification methodology that can be used to check the correctness of object code programs that implement the safety-critical control functions of DDD mode pacemakers. Our methodology is based on the theory of Well-Founded Equivalence Bisimulation (WEB) refinement, where both formal specifications and implementation are treated as transition systems. We develop a simple and general formal specification for DDD mode pacemakers. We also develop correctness proof obligations that can be applied to validate object code programs used for pacemaker control. Using our methodology, we were able to verify a control program with millions of transitions against the simple specification with only 10 transitions. Our method also found several bugs during the verification process.