Improved Mainlobe Interference Suppression Based on Blocking Matrix Preprocess

<table class="figure-group"><tr class="fig-image" id="a"><td><object data="https://static.hindawi.com/articles/jece/volume-2015/964901/figures/964901.fig.003a.svgz" name="964901.fig.003a" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(a) </b>Mainlobe direction and width</td></tr><tr class="fig-image" id="b"><td><object data="https://static.hindawi.com/articles/jece/volume-2015/964901/figures/964901.fig.003b.svgz" name="964901.fig.003b" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(b) </b>Maximum sidelobe level and nulling depth</td></tr></table>

<div>Mainlobe and sidelobe parameters (<a href="https://static.hindawi.com/articles/jece/volume-2015/964901/figures/#EEq1">1</a>).</div>

Journal of Electrical and Computer Engineering

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Figure 3

Figure 3: Improved Mainlobe Interference Suppression Based on Blocking Matrix Preprocess 