A Processor-Sharing Scheduling Strategy for NFV Nodes

<table class="figure-group"><tr class="fig-image" id="a"><td><object data="https://static.hindawi.com/articles/jece/volume-2016/3583962/figures/3583962.fig.007a.svgz" name="3583962.fig.007a" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(a) </b>Queue <svg height="12.9866pt" id="M135" style="vertical-align:-4.3507pt" version="1.1" viewbox="-0.0498162 -8.6359 21.0151 12.9866" width="21.0151pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M699 368C699 549 574 666 407 666C186 666 23 488 23 277C23 113 129 -3 288 -13L307 -26C431 -111 501 -139 533 -147C559 -154 613 -163 658 -164L666 -141C597 -111 507 -66 430 -11L416 -1C580 42 699 190 699 368ZM601 371C601 227 518 54 381 22L354 40L278 24C175 47 120 145 120 269C120 451 235 631 398 631C540 631 601 521 601 371Z" id="g113-82"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="722" vert-adv-y="722"></glyph.data></g><g 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id="g50-45"></path><glyph.data ascent="3443" descent="-2856" horiz-adv-x="237" vert-adv-y="237"></glyph.data></g><g transform="matrix(.0091,0,0,-0.0091,15.91,3.132)"><path d="M290 377C321 398 342 415 358 430C378 450 389 473 389 502C389 578 329 635 238 635H237C184 635 137 610 109 578L64 515L88 493C112 529 154 573 208 573S303 542 303 482C303 409 233 370 141 341L149 308C165 313 190 319 215 319C272 319 341 283 341 193C342 98 292 43 222 43C163 43 122 72 96 94C88 101 79 100 70 94C61 87 47 73 46 60C44 47 48 37 62 23C76 10 118 -12 165 -12C238 -12 430 62 430 223C430 297 379 359 290 375V377Z" id="g50-52"></path><glyph.data ascent="3443" descent="-2856" horiz-adv-x="487" vert-adv-y="487"></glyph.data></g></svg></td></tr><tr class="fig-image" id="c"><td><object data="https://static.hindawi.com/articles/jece/volume-2016/3583962/figures/3583962.fig.007c.svgz" name="3583962.fig.007c" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(c) </b>Queue <svg height="12.9866pt" id="M137" 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Journal of Electrical and Computer Engineering

A Processor-Sharing Scheduling Strategy for NFV Nodes

Figure 7