Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures

Table 11

Zoom coprocessor at 90 nm CMOS technology: characterization of the hybrid, clock, and power gated designs, achieved with the proposed automated flow. DAT_5%: area threshold 5%. DAT_10%: area threshold 10%. NA stands for not assigned and includes those LRs that placed in the always on domain.

Design	>Th	PG_set	CG_set	NA
DAT_5%	,
DAT_10%			,