Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures

Table 12

Zoom coprocessor at 90 nm CMOS technology: power gating overhead estimation step and clock gating overhead estimation step accuracy.

LR	PG saving%			Net	CG saving%			Net
	Est.	Real	Err.%	Err.%	Est.	Real	Err.%	Err.%
	−6.322	−6.331	0.15	0.18	−6.307	−6.313	0.09	0.17
	−23.464	−23.463	0.00	1.26	−23.369	−23.373	0.02	1.67
	−6.537	−6.544	0.10	1.65	−6.507	−6.514	0.10	1.59
	—	—	—	—	−0.958	−0.964	0.68	1.34
	—	—	—	—	—	—	—	—
	—	—	—	—	−0.870	−0.878	0.81	1.22
	—	—	—	—	−1.033	−1.039	0.63	0.15
	−7.062	−7.058	0.05	2.02	−6.987	−6.986	0.01	1.83
	—	—	—	—	−2.436	−2.443	0.27	1.55
	−5.498	−5.503	0.10	1.65	−5.474	−5.480	0.11	1.57
	—	—	—	—	−3.329	−3.285	1.32	3.67
	−4.278	−4.288	0.23	1.83	−4.267	−4.273	0.15	1.86
	—	—	—	—	−0.649	−0.656	1.01	1.13