Research Article
Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures
Table 13
Zoom coprocessor at 45 nm CMOS technology: characterization of the hybrid, clock, and power gated designs, achieved with the proposed automated flow. DAT 1%: area threshold 1%. DAT 5%: area threshold 5%. DAT_10%: area threshold 10%. NA stands for not assigned and includes those LRs that are placed in the always on domain.
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