Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures

Table 3

Parameter and power consumption of each LR, extracted by the synthesis reports of the baseline CGR platform.

Logic region	Kernel		Actors
		0.1	B	32	514	24
		0.6	D, E	32	8	8
		0.4	A, SB_0,	96	256	64
		0.3	F, G	32	265	192
Actor	Power [nW]
	lkg seq.	int seq	lkg comb.	int comb.
B	801	104987	121411	3916599	512	24
D	48	1104	51	319	4	4
E	56	1437	53	198	4	4
A	3264	89238	0	0	256	64
SB_0	0	0	307	409	—	—
SB_1	0	0	225	350	—	—
F	1232	22489	213	537	128	128
G	1385	44068	273	363	128	64