Hardware Efficient Architecture with Variable Block Size for Motion Estimation

Table 2

SAD output schedule for VBSME architecture.

Clock	Block	Size
1	0	4 × 4
2	1	4 × 4
3	0, 1	4 × 8
	2	4 × 4
4	3	4 × 4
5	2, 3	4 × 8
	4	4 × 4
6	0, 4	8 × 4
	5	4 × 4
7	6	4 × 4
	1, 5	8 × 4
	4, 5	4 × 8
	0, 1, 4, 5	8 × 8
8	7	4 × 4
	2, 6	8 × 4
9	8	4 × 4
	3, 7	8 × 4
	6, 7	8 × 4
	2, 3, 6, 7	8 × 8
	0, 1, 2, 3, 4, 5, 6, 7	8 × 16
10	9	4 × 4
11	10	4 × 4
	8, 9	4 × 8
12	11	4 × 4
13	12	4 × 4
	10, 11	4 × 8
14	13	4 × 4
	8, 12	8 × 4
15	14	4 × 4
	9, 13	8 × 4
	12, 13	4 × 8
	8, 9, 12, 13	8 × 8
	0, 1, 4, 5, 8, 9, 12, 13	16 × 8
16	15	4 × 4
	10, 14	8 × 4
17	11, 15	8 × 4
	14, 15	4 × 8
	10, 11, 14, 15	8 × 8
	8, 9, 10, 11, 12, 13, 14, 15	8 × 16
	2, 3, 6, 7, 10, 11, 14, 15	16 × 8
	Full macroblock	16 × 16