Hardware Efficient Architecture with Variable Block Size for Motion Estimation

Table 4

Comparison among VLSI implementations of VBSME architectures.

VBSME architecture	Search range	# of PEs	# of pixels	# of clock cycles to generate 41 SAD	# of clock cycles to generate MV	Frequency (MHz)	Frame processing rate (fps)	Technology	Gate count
Yap and McCanny [4]	32 × 32	16	1	281	4496	100	52 @CIF	130 nm	108k
Yap and McCanny [2]	32 × 32	16	1	262	4096	294	181 @CIF	130 nm	61k
Wei et al. [5]	33 × 33	256	16	40	1129	180	409 @CIF	180 nm	160k + 3.328 kB SRAM
							45 @720p
López et al. [6]	31 × 31	16	16	—	—	100	60 @CIF	250 nm	21.3k
Warrington et al. [7]	16 × 16	16	16	20	—	155	90 @SD	180 nm	155k
Kim and Park [3]	32 × 32	16	1	262	16384	416	256 @CIF	180 nm	39.2k
Ruiz and Michell [9]	32 × 32	64	4	65	1207	300	30 @1080p	180 nm	32.3k + 59 kB SRAM
Olivares [12]	32 × 32	256	16	—	4913	380.1	21.42 @1080p	130 nm	54k + 2.76 kB SRAM
Fatemi et al. [13]	32 × 32	256	4	90	5120	207	30 @SD	180 nm	31.5k
Tung et al. [14]	—	16	16	18	—	546.4	—	180 nm	149.2k
Parandeh-Afshar et al. [15]	—	4	4	64	—	285	—	130 nm	18k
Proposed	32 × 32	17	16	17	272	393.16	179 @1080p	130 nm	22k