Hardware Efficient Architecture with Variable Block Size for Motion Estimation

Table 5

Comparison among FPGA implementations of VBSME architectures.

VBSME architecture	Search range	# of PEs	# of pixels	# of clock cycles to generate 41 SAD	# of clock cycles to generate MV	Frequency (MHz)	Frame processing rate (fps)	FPGA	LUTs
Olivares [12]	32 × 32	256	16	—	4913	380.1	21.42 @1080p	Virtex 5	3768
Elhamzi et al. [16]	16 × 16	16	16	—	4096	436	13 @1080p	Virtex 6	1281
Parandeh-Afshar et al. [15]	—	4	4	64	—	285	—	Virtex 2	1431
Proposed	32 × 32	17	16	17	272	393.16	179 @1080p	Virtex 5	9486