Hardware Efficient Architecture with Variable Block Size for Motion Estimation

Table 6

Comparison of hardware and power efficiency for VBSME architectures.

Architecture	Frame processing rate (fps)	Gate count (k)	Power (mW)	TP in kMB/sec	in MB/sec/gate	in MB/sec/mW
Yap and McCanny [2]	181 @CIF	61	570 mW	71.676	1.175	125.75
Wei et al. [5]	409 @CIF; 45 @720p	163.32	423 mW	162	0.992	383
López et al. [6]	60 @CIF	21.3	—	23.76	1.11	—
Warrington et al. [7]	90 @SD	155	68 mW/70 kMB/s	324	2.09	1029.41
Kim and Park [3]	256 @CIF	39	—	101.38	2.6	—
Ruiz and Michell [9]	30 @1080p	91.3	115 mW	243	2.66	2113.04
Olivares [12]	21.4 @1080p	56.76k	314 mW	173.5	3.06	552.55
Fatemi et al. [13]	30 @SD	31.5	40.07 mW	108	3.43	2695.3
Parandeh-Afshar et al. [15]	—	18k	7.7 mW	9.615	0.53	1248.70
Proposed	179 @1080p	22k	540 mW	1449.9	65.9	2685