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Journal of Electrical and Computer Engineering
Volume 2016, Article ID 6123832, 8 pages
Research Article

Intermediate Frequency Digital Receiver Based on Multi-FPGA System

1Department of Electrical Engineering, College of Electronic Engineering, Chongqing University of Posts and Telecommunications, Chongqing, China
2Electrical and Computer Engineering, Faculty of Engineering and Applied Science, Memorial University, St. John’s, NL, Canada

Received 21 May 2016; Revised 23 September 2016; Accepted 28 September 2016

Academic Editor: Bin-Da Liu

Copyright © 2016 Chengchang Zhang and Lihong Zhang. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Aiming at high-cost, large-size, and inflexibility problems of traditional analog intermediate frequency receiver in the aerospace telemetry, tracking, and command (TTC) system, we have proposed a new intermediate frequency (IF) digital receiver based on Multi-FPGA system in this paper. Digital beam forming (DBF) is realized by coordinated rotation digital computer (CORDIC) algorithm. An experimental prototype has been developed on a compact Multi-FPGA system with three FPGAs to receive 16 channels of IF digital signals. Our experimental results show that our proposed scheme is able to provide a great convenience for the design of IF digital receiver, which offers a valuable reference for real-time, low power, high density, and small size receiver design.