DPFFs: <svg xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg" style="vertical-align:-0.3069pt" id="M1" height="15.5593pt" version="1.1" viewBox="-0.0657574 -15.2524 54.0725 15.5593" width="54.0725pt"><g transform="matrix(.017,0,0,-0.017,0,0)"><path id="g190-68" d="M614 175C564 76 510 21 408 21C256 21 146 149 146 336C146 488 235 629 402 629C510 629 570 586 597 480L626 488C620 541 614 582 606 638C578 643 510 665 429 665C206 665 44 527 44 316C44 157 153 -15 402 -15C474 -15 558 5 586 11C604 45 629 119 643 165L614 175Z"/></g><g transform="matrix(.012,0,0,-0.012,11.454,-7.578)"><path id="g190-243" d="M411 139C381 76 368 73 314 73H129L267 224C351 317 400 380 400 469C400 574 322 635 233 635C176 635 128 610 98 576L40 495L63 476C89 515 130 568 198 568C274 568 316 519 316 436C316 347 251 264 191 192C142 134 85 76 30 21V0H403C415 45 425 89 438 131L411 139Z"/></g><g transform="matrix(.017,0,0,-0.017,17.718,0)"><path id="g190-78" d="M861 0V28C774 35 771 41 768 147L759 509C756 612 762 614 851 622V650H681L449 149L221 650H57V622C148 613 153 609 144 479L130 271C123 166 117 123 111 88C104 46 85 34 26 28V0H259V28C192 35 169 42 167 90C166 130 166 173 170 256L185 541H187L411 7H431L675 555H679L683 147C683 41 680 35 598 28V0H861Z"/></g><g transform="matrix(.017,0,0,-0.017,32.852,0)"><path id="g190-80" d="M381 665C170 665 44 498 44 318C44 125 188 -15 369 -15C552 -15 703 117 703 333C703 534 550 665 381 665ZM359 629C491 629 601 517 601 306C601 114 502 21 390 21C249 21 146 158 146 346S248 629 359 629Z"/></g><g transform="matrix(.017,0,0,-0.017,45.672,0)"><path id="g190-84" d="M409 504C401 567 396 607 392 642C354 654 312 665 266 665C137 665 60 583 60 487C60 374 161 325 225 290C300 250 355 215 355 141C355 68 311 21 235 21C131 21 86 122 71 183L41 176C48 128 61 42 68 21C78 16 93 8 118 0C142 -7 175 -15 216 -15C349 -15 438 69 438 174C438 287 344 333 265 374C186 414 138 449 138 522C138 576 172 631 249 631C336 631 363 562 380 499L409 504Z"/></g></svg> Direct Path Flip-Flops for Process-Resilient Ultradynamic Voltage Scaling

<table class="figure-group"><tr class="fig-image" id="a"><td><object data="https://static.hindawi.com/articles/jece/volume-2016/8268917/figures/8268917.fig.009a.svgz" name="8268917.fig.009a" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(a) </b>Photograph and GDS layout view</td></tr><tr class="fig-image" id="b"><td><object data="https://static.hindawi.com/articles/jece/volume-2016/8268917/figures/8268917.fig.009b.svgz" name="8268917.fig.009b" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(b) </b>FF test circuits</td></tr></table>

<div>Test chip with isolated FF test circuits in 130 nm technology.</div>

Journal of Electrical and Computer Engineering

fig9

Figure 9

Figure 9: DPFFs: <svg xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg" style="vertical-align:-0.3069pt" id="M1" height="15.5593pt" version="1.1" viewBox="-0.0657574 -15.2524 54.0725 15.5593" width="54.0725pt"><g transform="matrix(.017,0,0,-0.017,0,0)"><path id="g190-68" d="M614 175C564 76 510 21 408 21C256 21 146 149 146 336C146 488 235 629 402 629C510 629 570 586 597 480L626 488C620 541 614 582 606 638C578 643 510 665 429 665C206 665 44 527 44 316C44 157 153 -15 402 -15C474 -15 558 5 586 11C604 45 629 119 643 165L614 175Z"/></g><g transform="matrix(.012,0,0,-0.012,11.454,-7.578)"><path id="g190-243" d="M411 139C381 76 368 73 314 73H129L267 224C351 317 400 380 400 469C400 574 322 635 233 635C176 635 128 610 98 576L40 495L63 476C89 515 130 568 198 568C274 568 316 519 316 436C316 347 251 264 191 192C142 134 85 76 30 21V0H403C415 45 425 89 438 131L411 139Z"/></g><g transform="matrix(.017,0,0,-0.017,17.718,0)"><path id="g190-78" d="M861 0V28C774 35 771 41 768 147L759 509C756 612 762 614 851 622V650H681L449 149L221 650H57V622C148 613 153 609 144 479L130 271C123 166 117 123 111 88C104 46 85 34 26 28V0H259V28C192 35 169 42 167 90C166 130 166 173 170 256L185 541H187L411 7H431L675 555H679L683 147C683 41 680 35 598 28V0H861Z"/></g><g transform="matrix(.017,0,0,-0.017,32.852,0)"><path id="g190-80" d="M381 665C170 665 44 498 44 318C44 125 188 -15 369 -15C552 -15 703 117 703 333C703 534 550 665 381 665ZM359 629C491 629 601 517 601 306C601 114 502 21 390 21C249 21 146 158 146 346S248 629 359 629Z"/></g><g transform="matrix(.017,0,0,-0.017,45.672,0)"><path id="g190-84" d="M409 504C401 567 396 607 392 642C354 654 312 665 266 665C137 665 60 583 60 487C60 374 161 325 225 290C300 250 355 215 355 141C355 68 311 21 235 21C131 21 86 122 71 183L41 176C48 128 61 42 68 21C78 16 93 8 118 0C142 -7 175 -15 216 -15C349 -15 438 69 438 174C438 287 344 333 265 374C186 414 138 449 138 522C138 576 172 631 249 631C336 631 363 562 380 499L409 504Z"/></g></svg> Direct Path Flip-Flops for Process-Resilient Ultradynamic Voltage Scaling 

Journal of Electrical and Computer Engineering

DPFFs: Direct Path Flip-Flops for Process-Resilient Ultradynamic Voltage Scaling

Figure 9