DPFFs: Direct Path Flip-Flops for Process-Resilient Ultradynamic Voltage Scaling

Table 2

Delay sensitivity over variation (measured).

Voltage [V]	Clock-to-Q rise/fall delay [ns]
	MTGFF	C2FF	C2DPFF	TGDPFF
1.15	0.185/0.174	0.172/0.1692	0.136/0.130	0.142/0.139
1.10	0.208/0.197	0.198/0.1911	0.155/0.149	0.165/0.162
1.05	0.237/0.227	0.229/0.2199	0.179/0.174	0.195/0.191
1.00	0.279/0.265	0.262/0.2580	0.210/0.208	0.236/0.229
0.95	0.331/0.317	0.318/0.3018	0.250/0.240	0.288/0.281
0.90	0.411/0.393	0.392/0.3825	0.316/0.322	0.365/0.358
0.85	0.525/0.514	0.532/0.5094	0.417/0.431	0.482/0.479
0.80	0.726/0.716	0.746/0.7058	0.658/0.674	0.671/0.681
0.75	1.091/1.086	1.126/1.0961	0.962/1.011	0.978/1.025
0.70	1.916/1.864	1.975/1.8429	1.674/1.704	1.649/1.711
0.65	3.543/3.448	3.657/3.4009	2.954/2.807	2.905/2.853
Ratio	19.1/19.8	21.2/20.1	21.7/21.5	20.4/20.5

Test condition: SS/25°C.
Ratio (%) = delay at 0.65 V/delay at 1.15 V.