On Improving the Performance of Dynamic DCVSL Circuits

Table 4

Leakage power (nW) in TG-EDCVSL and TG-EDCVSL-LCT three-input XOR-XNOR gates.

Inputs			Architecture
A	B	C	TG-EDCVSL	TG-EDCVSL-LCT	Reduction with respect to TG-EDCVSL (%)
90 nm node
0	0	0	9.8	4	59
0	0	1	0.34	0.21	64
0	1	0	0.34	0.21	64
0	1	1	9.8	4	59
1	0	0	0.34	0.21	64
1	0	1	9.8	4	59
1	1	0	9.8	4	59
1	1	1	0.34	0.21	64
65 nm node
0	0	0	14	5.07	63
0	0	1	0.38	0.26	66
0	1	0	14	5.07	63
0	1	1	0.38	0.26	66
1	0	0	0.38	0.26	66
1	0	1	14	5.07	63
1	1	0	14	5.07	63
1	1	1	0.38	0.26	66
45 nm node
0	0	0	24.5	5.85	76
0	0	1	0.43	0.12	72
0	1	0	0.43	0.12	72
0	1	1	24.5	5.85	76
1	0	0	0.43	0.12	72
1	0	1	24.5	5.85	76
1	1	0	24.5	5.85	76
1	1	1	0.43	0.12	72