Abstract
A high-input voltage 2-phase series-capacitor (2-pscB) DC-DC buck converter is theoretically analyzed, designed, and implemented. A new design approach for an automatic current sharing scheme was presented for a 2-phase series-capacitor synchronous buck converter. The series-capacitor voltage is used to achieve current sharing between phases without a current sensing circuit or external control loop as each phase inductor charges and discharges the series capacitor to maintain its average capacitor voltage constant. A novel isolated gate driver circuit to accommodate an energy storage capacitor is proposed to deliver isolated gate voltages to the switching transistors. An I2 control scheme that uses only one feedback path control for the four gate drivers is proposed to enable higher voltage conversion. An experimental 110-12 V 6 A load prototype converter was designed, and its current sharing characteristics were experimentally verified.
1. Introduction
Two-phase series-capacitor buck converters were introduced to power laptops as low-voltage, high-current voltage regulator modules (VRMs) as well as nonisolated point-of-load (POL) converters [1–3]. Automatic current sharing is important to distribute heat generation in multiphase switching topologies at full load without the need to use current sensing circuit or external control loop between phases. Current sharing implementation for multiphase switching converter topologies is reported in [4–8]. The automatic current sharing concept is the main feature of this double step-down buck topology where the series capacitor was utilized to accomplish current sharing. 2-pscB is a unique converter topology that combines the benefits of a switch capacitor circuit as a DC source and a two-phase buck converter [9–11]. Usually, these converters are used as low-voltage (<12 V) POL voltage regulators [12].
In this work, a high-voltage input (110 V) 2-pscB converter is theoretically analyzed, designed, and implemented to examine the capability of current sharing at a higher voltage level and its impact on overall efficiency [13]. A new design methodology, without using fudge factors or constants compared to previous designs [14], is used to implement an automatic current sharing scheme. The practical implementation of the 2-pscB converter is a challenging task due to the complexity of gate driver galvanic isolation due to timing mismatch between phase A switches. The two conventional bootstrap structures as shown in paper [1] are unsuitable for higher input voltages, and bootstrap diode isolation is not adequate to provide stability to gate driver reference voltage because voltage swing is common due to charging and discharging of the series capacitor between the phase A gate drivers. A new isolated gate driver circuit to accommodate an energy storage capacitor is proposed to deliver isolated gate voltages to the switching transistors. An I2 control scheme that enables higher voltage conversion is proposed that uses only one feedback path control to drive the 4 gate drivers. An experimental 110-12 V at 6 A load prototype converter was designed, and its current sharing characteristics were experimentally verified to show that a higher input voltage is possible compared to low input voltage [14, 15] using an integrated circuit controller driving internal FETs of TPS54A20. Figure 1(a) shows the two-phase series-capacitor buck converter with automatic current sharing.
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The outline of the paper is as follows. Section 2 describes the fundamentals of this topology. Section 3 derives the main parameters for the 2-pscB converter. Section 4 describes the isolated gate driver circuit design. Section 5 presents the proposed control scheme. Section 6 presents the simulation results using LTspice. Section 7 shows the experimental prototype and characterization results to illustrate the functionality and performance of the 2-pscB converter. Sections 8 and 9 provide discussion and the summary.
2. Analysis of the 2-pscB Converter
A 2-pscB converter has four switching intervals: the first switching interval D1T with Q11 and Q22 switching on, the second and fourth switching intervals D2T and (1 − d3)T with Q12 and Q22 switching on, and the third switching interval D3T with Q12 and Q21 switching on. Figure 1(b) shows the four switching intervals and the switching devices that are switched on during these intervals. Hence,where T is the switching period. At steady state, during the first switching interval, the high-side switch of phase A, switch Q11, is switched on, and the inductor current flowing through inductor L1 charges the series capacitor Cs [3, 9]. The duty cycle is given aswhere , , and represent switching intervals for the series-capacitor buck modes. When these intervals are the same, = = = D. Hence,
To achieve the current sharing balance between the two phases, the switching voltage nodes must be the same. Hence,
From equations (2) and (4) at steady-state conditions,
3. Derivation of Design Parameters
A new design approach for an automatic current sharing scheme is presented for the 2-pscB converter. The series-capacitor voltage is used to achieve current sharing between phases without a current sensing circuit or external control loop as each phase inductor charges and discharges the series capacitor to maintain its average capacitor voltage constant. Design parameters are derived and experimentally validated.
The main switches of both phases are driven at 180° phase shifts and with a duty ratio of less than 50%. The inductor currents are defined aswhere and are the maximum and minimum values of phase A and B inductor currents. and are the average load currents at phase A and B, respectively. In this 2-pscB converter, the total average output inductor current is the sum of both the average phase inductor currents. For a complete current sharing, the peak-to-peak ripple current of a single phase iswhere . As such, a larger L and smaller Ton will yield a smaller ripple current. The total average output current in terms of will be
The total inductor current at zero condition is equal to the minimum value , when Q11 is off in modes II and IV:When the load current contributed by each phase is at complete current sharing condition, = = , the maximum inductor current value will be at full charging of series capacitor in phase A and at fully discharging in phase B.
Thus, the peak-to-peak inductor current ripple iswhere is phase A or B average current ripple at full current sharing. At continuous current mode (CCM) operation, is a positive value. During current sharing, when , , we have
The critical value for the two-phase inductors is then
The phase inductance should be within 1.5 to 2 times the critical inductance given in equation (14) to yield a good efficiency. Note that the efficiency of the converter increases with increasing inductance with performance degradation in its transient response. To avoid this effect, the inductance value should be chosen to provide reasonable efficiency and good transient response. As such, the output inductor value can be expressed in terms of its current ripple as
The instantaneous capacitor charge stored in one half of the switching period can be used to determine its output capacitance value as shown in Figure 2.
Hence, during a complete current sharing,
Using the maximum and minimum output capacitor current expressions:
For smaller output capacitor parasitic resistance and smaller , .
Series-capacitor voltage, , acts as an internal feedback loop quantity to adjust the current sharing for the two phases. As such, if the inductor currents are not equal, the series-capacitor voltage would drift up or down and a smooth charging balance could not be maintained [16, 17]. This is because the average capacitor voltage remains constant only when the charge and discharging period balance exists. Inductor currents iL1 and iL2 charge and discharge the series capacitor Cs, respectively. Figure 3 shows a simplified mathematical representation of 2-pscB converter with its internal current sharing mechanism resulting from the series-capacitor voltage including parasitic components. In steady-state conditions during automatic current sharing, the two inductor currents should be equal, and then the average series capacitor voltage will be constant as well with approximately half the input voltage across it, and the series capacitor acts as a dc voltage source for the third interval. Hence,
Using the iCs waveform shown in Figure 4, if can be neglected, the minimum Cs value can be generalized and expressed at complete current sharing as
The above equations enable design parameters such as Cs, Co, and ∆iL to be determined.
One of the technical advantages of multiphase is that the combined output ripple (total ripple) is less than the ripple current in each inductor (phase ripple). This occurs due to driving the phases out of phase. In case of the 2-pscB converter at interleaving, the phases with a proper timing circuitry, ripple current reductions can be easily achieved even under unbalanced current sharing since the series-capacitor voltage can compensate for the current difference for certain limits that results in much less output voltage ripple. Assuming all the ripple voltage is caused by the capacitance of the output capacitor, the approximated peak to the peak value of the total output current ripple to be filtered by the output capacitor iswhere is output current ripple cancellation multiplier, N is the number of the phases, and floor function returns the greatest integer value less than the argument.where , .
Figure 5 shows that at certain duty cycle (D) value, there is a total cancellation of the ripple current according to the above constraints. For example, total ripple current cancellation for a 2-phase converter occurs beyond a duty cycle of 0.25, whereas for a 4-phase converter, this total ripple current cancellation occurs at duty cycle beyond 0.125 and between a duty cycle of 0.25 and 0.375 as shown in Figure 5.
4. A Novel Isolated Gate Driver
Figure 6 shows the gate driver circuit using a UCC27531 gate driver to accommodate adding a series capacitor between switches Q11 and Q12 of the phase A [18], where the gate reference voltage for the isolated high-side switch is the positive side of Cs, whereas the gate voltage for the low-side switch circuit requires a different isolation loop since its reference voltage is ground. As such, an isolation scheme must encompass the entire high-side switch circuit because inserting a series capacitor will introduce a time delay between the gate voltages of the two switches.
This will interfere with the synchronization of the switching time and voltage level. Isolation scheme is required to isolate the ground loops; this means there should be no direct conduction path between the high-side driver and the synchronous rectifier switch driver due to the voltage storage element of Cs. The anode of bootstrap diodes, DBstrap1, is commonly connected to a driver source VDD. Therefore, bootstrap capacitors C5 to C8 are charged by a voltage difference between the driver source voltage VDD and the series-capacitor voltage VCs during the on-times of the Q12 switch through the bootstrap diode DBstrap1. Since the four bootstraps diodes are isolated using an isolated DC source, the gate voltages of the main switches Q11 and Q21 are enough to charge the bootstrap capacitors. As such, phase B uses the same gate drivers as phase A. To reduce the cost of the four matched bootstrap capacitors for each gate driver, C5 to C8, two of them can be eliminated. For voltage higher than 12 V, external FETs are used for better heat distribution and isolation [15]. The gate driver should be located as close to the MOSFETs as possible. In this way, self-inductance and self-resistance of the traces will be reduced to minimize voltage spikes and reduce EMI. For a complete current sharing, dead time must be the same for both phases. In the proposed circuit, there are two ways to adjust the dead time between the high-side signal and low-side signal using two variable resistors before and after the optocoupler. Current sink loops for the high-side switches are not similar in each phase as illustrated in Figure 7. dV/dt occurs on the MOSFET drain when the MOSFET is already held in its off state by the gate driver. The current created by this dV/dt charges the Cgd Miller capacitance and is shunted by the pull-down stage of the driver.
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If the pull-down impedance is not sufficiently low, then a voltage spike can appear in the Vgs of the MOSFET. The upper limit for the voltage at the EN node is 5 V. This complete gate circuit contains 4 bootstrap diodes at the output terminals of the power supply fly-back transformer.
5. An I2 Control Scheme for 2-pscB Converter
The objective of the feedback compensation loop is to enable its closed-loop converter to possess adequate line and load regulations with a low output voltage overshoot. Multiphase current sharing two loops control was proposed in [19, 20]. Converter control to output transfer function at full current sharing iswhere
To obtain a well-regulated average output voltage signal, switching frequency must be greater than ten times the resonant frequency for small output voltage ripple ( recommended). The natural output impedance (Zout) of output filter peaks at the converter resonant frequency (fo = 12 kHz). Therefore, the unity-gain crossover frequency (fc) must be higher than the resonance frequency to yield a sufficient gain margin to suppress its ringing effect, maintain constant series-capacitor voltage, and obtain a sufficient phase margin. If the equivalent series resistance (ESR) of the capacitor that dominates its impedance at higher frequencies is neglected, then the peak resonance occurs atwhere is the characteristic impedance of the filter.
For a converter that has a long series capacitance charging period, an enhanced I2 current control scheme is used to compare the sum of the output current (with a current sensing gain Zi) and analog current of its output voltage feedback line (with a current sensing gain Zv) to the output voltage of the compensated error amplifier. The enhanced I2 control can achieve a fast load transient response at a constant frequency. The equivalence series resistance (ESR) of the output capacitors or iL is used as the current sensing resistor as shown in Figure 8(a) where the inner loop uses the inverting input signal voltage Vsense across the sensing resistor Rs generated by both output current io and feedback as a proportional feedback control variable and the outer loop uses the control signal VC generated by compensating the errors between the output voltage and the reference voltage Vref in the error amplifier. The sensing voltage Vsense in the inner loop contains the information of both the feedback output voltage and inductor current when Vsense reaches the value of VC. The comparator changes the state at its output u(t) which compares with the oscillator ramp signal r(t) at twice the switching frequency. This allows the logic latch circuit to generate two pulses at half the oscillator frequency. The logic latch and delay time circuit consist of logic gates and galvanic isolation of (10–50) MBd to produce four signals with a maximum 50% duty cycle that can be controlled by only DDrive signal variations. An RC inverting negative feedback circuit can be added to the current regulator (comparator) to accurately control the overall current regulator gain. The error amplifier uses a PID compensator with a Vref of 1.25 V.
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A single feedback control loop with one modulator for the two phases gives several advantages over conventional schemes [7, 13, 19] such as immunity against sensing inaccuracies which potentially reduces the complexity and the number of components and size of the controller and minimizes the time propagation delay and voltage drop to enable the generation of two duty cycle pulses D1 and D3 within one ramp signal period. As such, no offline or online calibration is needed to achieve optimum efficiency. Figure 8(b) shows the waveforms within the compensator loop where , .
As shown in Figure 9, the ramp signal frequency is twice the converter switching frequency to generate two-phase pulses. During a step response, the controller decreases the current passing through the load to minimize the current surge as seen in Figure 10(a). As can be seen, a low overshoot voltage is due to fast-direct feedback loop action where series-capacitor charging starts instantaneously at zero time; at the same time, its soft start feature allows the output voltage to ramp up in a controlled manner minimizing output voltage overshoot during startup as shown in Figure 10(b). The step response has only a small effect on maintaining automatic current sharing balance as shown in Figure 10(c), where iL1 is decreased by switching off Q11 to achieve a predetermined overshoot voltage magnitude as well as to enable the soft start feature. As such, it eliminates the need to monitor and precharge the series-capacitor voltage. The simulated Matlab waveforms shown in Figure 10 verify the analytical and design methods.
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6. Simulation Work
Using derived equations (12) to (22), the converter parameters for the desired load and output ripples are determined. The specifications for the 110/12 V dc 2-pscB converter are listed in Table 1. A two-phase series-capacitor buck converter is simulated using LTspice. The simulation efficiency reaches 98.7% for a perfect dead time implementation in the steady-state operation.
Figure 11(a) shows the waveforms for Vds and Ids of Q11 during the D1T interval. As can be seen, both Vds and VCs are 55 V. Its drain current, which is also the phase A inductor current, increases linearly to charge the series capacitor to its maximum voltage. Figure 11(b) shows the switching losses of Q11. Current spikes occur during the switching transitions of both Q11 and Q22. The total switching losses are 40 W during a 4 ns switching period. Figure 11(c) shows where the gate currents are less than 1.5 A and 2.5 A during the rising and falling edges of the gate pulses.
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Figure 12 shows the series-capacitor voltage, current, and two-phase inductor current waveforms during steady-state operation. As can be seen from Figure 12(a), the average VCs maintains its value at exactly half of the input voltage with a voltage ripple of less than 0.5 V. The output voltage ripple can be controlled by the size of the output filter. The average charging and discharging currents for the series capacitor are similar as shown in Figure 12(b); this verifies the steady-state operation of the 2-pscB converter. Figure 12(c) shows the inductor currents iL1 and iL2; the two inductor currents have identical magnitudes, and they are 180° out of phase at steady-state operation.
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7. Experimental Results
The component selections for the 2-pscB converter are first justified. For a 2.54 cm long and 40-mil wide printed circuit board (PCB) copper trace, the parasitic inductance is about 8 nH. The parasitic inductance of a 0.4 mm diameter via a 1.6 mm thick PCB is 1.2 nH [21, 22]. The self-resistance calculations of all traces are performed using the Autodesk Eagle software. The parasitic resistance, rCs, can be reduced to half the value by using two parallel aluminum electrolytic capacitors of 4.5 µF with a dissipation factor of 0.3 for the two series capacitors Cs1 and Cs2. The total ESR of the two parallel capacitors is
Two ERU (16) helically wound choke inductors with a DC resistance of 3.7 mΩ and a current saturation of 18.3 A are used for the phase inductors. A total of four IPB530N15N3 power MOSFETs are required to implement the 2-pscB, and an additional power MOSFET (Si7898) is used for the fly-back converter to provide or serve as a component power supply as shown in Table 2 [23].
This fly-back converter is used to supply four isolated 18V to drive the gate of four MOSFETs at a frequency of 323 kHz. A Tektronix P5200 Differential Probe 50X/500X attenuation was used to measure voltages as shown in Figure 13. The evaluation model (EVM ) input 5 V PWM signal with twice the switching frequency and a double duty cycle to generate four signals through the latch circuit. Input signal and phase A generated gate driver signals are shown in Figure 14. The input PWM signal (DDrive) will be at 500 kHz at 50% duty or less to generate four signals at 250 kHz at 25% duty cycle or less. As such, controlling the four gate signals becomes easier and can be achieved with only the main input PWM signal. Signal delay time between the optocoupler input and MOSFET gate is measured to be 170 ns which includes the rise time and first propagation delay time as shown in Figure 15. The time delay is 57 ns to include both the fall and second propagation delay times. This difference is caused by the PCB conductors which can be reduced by a better PCB layout as well as a multilayer structure to separate the power conductors from the ground conductors. To achieve the required dV/dt, the gate driver must deliver the gate charge in 20 ns or less. This means a gate current of = 3 nC/20 ns = 0.15 A or higher is needed. However, the MOSFET gate-source current reaches 1.2 A and the sink current is less ( = 3 nC maximum, = 20 V/ns) as shown in Figure 16 which is almost similar to the simulated gate current value for a (on) (ext.) = 2 Ω, (off) (ext.) = 0 (Figure 11(c)). Figure 17 exhibits the typical waveforms of versus for MOSFET Q21 of phase B. Figure 18 shows the node voltages and at a switching frequency of 250 kHz. As can be seen, these node voltages have a variation of within 0.5 V. As stated earlier, these node voltages must be the same at full current sharing. Any difference or any small variation is caused by dead time, trace width, and length unbalance of the two phase paths or it can be the result of switching speed due to the different charging and discharging time for the MOSFET’s input capacitors (Cgs). Since the switch node voltage slope is caused by the load current, as such, the slope of is affected by the charging period of both Cs and Co. This is because charges only Co, and then a slope difference can be seen. To eliminate this difference, the value of Cs must be chosen carefully in terms of inductance variations, zero dc bias inductance, saturation profiles, and converter layout and Cs position.
Figures 19 and 20 show the series-capacitor current, iCs, and inductor currents, iL1 and iL2, at a resistive load current of 2.4 A, respectively. The phase A inductor current (iL1) has a slightly higher peak-to-peak ripple, due possibly to slope difference and converter layout parasitic inductance. The maximum efficiency achieved from this prototype converter is 92% at a load current of 3.38 A and an input current of 442 mA despite the peak-to-peak ripple of about 270 mA due to charging and discharging of both Cs and Co. Prototype is shown in Figure 21. Maximum output power of 73 W with an efficiency of 91% was achieved at a full load current of 6 A. The experimental and simulated efficiency results are illustrated in Figure 22.
8. Discussion
Due to PCB trace drop voltages and layout mismatch of the two phases, there is an expected small variation between the simulation and measured efficiency results. Moreover, wires and component parasitic circuit elements also have a negative impact. Dissipation curves show a normal increase with increasing load currents. Even though there is a small trace resistive unbalance between the two phases, its current sharing mechanism is still functioning well. Because of the above, the node voltage at Vsw2 is nearly 0.5 V less than that at Vsw1. Otherwise, losses are very low when current sharing condition is achieved. For some cases, to reduce losses and provide protection to the MOSFET switches, there is a need to add time delay control circuit to precharge the series capacitor to half of its nominal voltage to protect the converter and reduce the charging current surge before switching on the converter.
Using only one PWM signal input of the latch logic circuit may give an advantage for the closed-loop circuit and simplify the control scheme where the control loop frequency and duty cycle should be twice the actual switching frequency. Since the main switches of both the phases are driven at 180o phase shift and with a duty ratio of less than 50%, a push-pull controller can be implemented to achieve this range. Note that the other two MOSFETs for the synchronous rectifier switches (lower side) are just complementary switches. According to Ampere’s Law, the physical phase current loop forms a magnetic field in proportion to the output shared current and the phase loop area. This field can couple with other circuit loops such as control circuit (per Faraday’s law) with more coupling at higher frequencies, resulting in harmful crosstalk. But this is not the case of this topology since the first and the third mode current loops are nearly opposite in direction and the field will be cancelled out. In this circuit, there is tendency to avoid extra “band-aid” circuitry like snubbers to reduce line current distortion and losses. The proposed 2-pscB converter shows a good performance suitable for high-frequency dc/dc applications with high step-down ratios such as those in EV dc power converters and laptop power suppliers. These applications are restricted by physical size, heat dissipation, and inductor variations.
9. Summary
A new theoretical approach to design an automatic current sharing scheme was presented for a 2-phase series-capacitor synchronous buck converter. The effects of its phase unbalance and parasitic circuit elements were discussed. An I2 current feedback controller was used to regulate the output voltage as well as to balance the two-phase inductor currents.
Experimental results were presented for an 110 V/12V, 6A, 250 kHz 2-pscB converter with a new multiphase isolated gate driver.
Data Availability
The simulation and experimintal data used to support the findings of this study are available from the corresponding author upon request.
Conflicts of Interest
The authors declare that there are no conflicts of interest regarding the publication of this paper.