An Efficient Design of QCA Full-Adder-Subtractor with Low Power Dissipation

Figure 1

(a) The four-phase clocking scheme. (b) The logical states defined by the electron configuration for the QCA cell consisting of four quantum dots, (c) A binary wire that can be achieved by two cell layouts. (d) The majority gate with three inputs and the single output with a binary state decided by majority voting behaviour, (e) The Inverter that is achieved by placing the two cells diagonally.

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(b)

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