An Efficient Design of QCA Full-Adder-Subtractor with Low Power Dissipation

Table 1

Full subtractor comparison.

Subtractor circuit	Area (μm^2)	Cell count	Latency
Ref [32]	0.205	178	8
Ref [33]	0.168	136	7
Ref [34]	0.1043	104	7
Ref [22]	0.0287	32	2
Proposed full subtractor	0.01	20	2