An Efficient Design of QCA Full-Adder-Subtractor with Low Power Dissipation

Table 2

Full adder comparison.

Adder circuit	Area (μm^2)	Cell count	Latency
Ref [35]	0.206	198	N
Ref [36]	0.144	135	1.5
Ref [37]	0.146	105	0.75
Ref [38]	0.0875	95	2.25
Ref [39]	0.0876	93	1.25
Ref [40]	0.0801	73	0.75
Ref [41]	0.044	73	0.75
Ref [42]	0.0434	59	1
Ref [43]	0.034	51	0.75
Ref [44]	0.042	49	1
Ref [45]	0.035	46	1
Proposed full adder	0.01	19	0.5