A Block-Based and Highly Parallel CNN Accelerator for Seed Sorting

<table class="table-group" id="tab5"><tr><td><table class="table"><tr><td class="thead-hr" colspan="4"><hr/></td></tr><tr class="thead"><td class="align_left">Resources</td><td class="align_center">Utilization</td><td class="align_center">Available</td><td class="align_center">Percent (%)</td></tr><tr><td class="thead-hr" colspan="4"><hr/></td></tr><tr><td class="align_left">DSP</td><td class="align_center">207</td><td class="align_center">220</td><td class="align_center">94</td></tr><tr><td class="align_left">BRAM</td><td class="align_center">128</td><td class="align_center">140</td><td class="align_center">91</td></tr><tr><td class="align_left">LUT</td><td class="align_center">41622</td><td class="align_center">53200</td><td class="align_center">79</td></tr><tr><td class="align_left">FF</td><td class="align_center">47331</td><td class="align_center">106400</td><td class="align_center">46</td></tr><tr class="table-tr"><td colspan="4"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

<div>Resource utilization of FPGA under optimal parameter configuration.</div>

Journal of Electrical and Computer Engineering

tab5

Table 5

Table 5: A Block-Based and Highly Parallel CNN Accelerator for Seed Sorting 