Table 1: Overview of major reliability challenges due to technology scaling of charge storage NVM.

Reliability challenges due to technology scaling of charge storage NVMReferences

1Vt distribution broadening and shifting due to cell level Vt instability mechanisms, such as charge loss, charge gain, and RTN. These mechanisms exacerbated along technology scaling[8396]
2Neighboring bit interference (disturb phenomenon) that inadvertently alters Vt of neighboring cell while erase/program/read on an other memory cell[9799]
3FG interference to adjacent memory cell of standard FG flash memory[100]
4Decrement in tolerable loss of electrons in storage layer due to shrinkage in cell’s dimension as shown in Figure 2[9]
5Program interference caused by cell-to-cell interference of adjacent word line[101]
6Adjacent bit line cell interference due to RTN on 32 nm NAND flash[102]
7Limitation on thickness of tunnel oxide layer > 8 nm for FG flash memory to prevent severe defect assisted charge leakage or Flash-SILC[103107]
8Limitation on gate coupling ratio of GCR > 0.6 for control gate to properly regulate the channel for FG flash memory[106]
9Edge word line disturb exhibited by FG NAND memories[108]
10Variability effect of Vt distribution of nanoscale NAND memories[109]
11Cell-to-cell coupling interference ratio was found to be inversely proportional to design rules of 2D memory structure that includes FG and charge trap flash (CTF) structures; as shown in Figure 3, 2D memory structure will hit the design limit for coupling interference ratio of 5 at approximately 16 nm[8]