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Journal of Nanomaterials
Volume 2013 (2013), Article ID 560252, 5 pages
Research Article

An Analytic Model for Estimating the Length of the Velocity Saturated Region in Double Gate Bilayer Graphene Transistors

1Faculty of Electrical Engineering, Universiti Teknologi Malaysia (UTM), Johor Bahru, 81310 Johor, Malaysia
2Department of Electrical Engineering, IAU, Yasooj Branch, Yasooj 7591483587, Iran
3Centre for Artificial Intelligence and Robotics (CAIRO), Universiti Teknologi Malaysia (UTM), 54100 Kuala Lumpur, Malaysia
4Malaysia-Japan International Inst. of Technology, Universiti Teknologi Malaysia (UTM), 54100 Kuala Lumpur, Malaysia

Received 1 August 2013; Revised 7 October 2013; Accepted 8 October 2013

Academic Editor: Zhenhui Kang

Copyright © 2013 M. Saeidmanesh et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


An analytical model for surface potential of asymmetric double gate Bilayer Graphene (BLG) transistors is presented on the basis of two-dimensional Poisson’s equation. To verify the accuracy of potential model, the modelling data are compared with the simulation data of FlexPDE program and a good agreement is observed. From surface potential expression, the device behaviour in velocity saturation region is investigated. As a result, lateral electric field and length of velocity saturation region () are formulated and their dependence on several device parameters is carefully examined.