Carbon Nanotubes for Thin Film Transistor: Fabrication, Properties, and Applications
Figure 17
View of well-aligned SWCNT-TFT. (a) Schematic of the device. Aligned SWCNTs were synthesized on the quartz substrate at 900°C. Source, drain, and gate electrodes were deposited ITO at room temperature with HfO2 gate dielectric. (b) SEM image of aligned SWCNT arrays [67].
