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Journal of Nanomaterials
Volume 2014 (2014), Article ID 203963, 5 pages
Research Article

Novel BCD Process Platform with Integrated Self-Extracted JTE Trench Technology for EL Drivers ICs

1The 58th Research and Scientific Institute, China Electronic Technology Group Corporation, Wuxi 214035, China
2Guangxi Experiment Center of Information Science, Guilin University of Electronic Technology, Guilin 541004, China

Received 25 March 2013; Accepted 7 August 2013; Published 2 January 2014

Academic Editor: Hua-Liang Zhang

Copyright © 2014 Wei Huang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A low cost silicon BCD technology in place of high cost SOI BCD technology for monolithic integrated EL driver ICs application is put forward. Several key technologies are presented. An advanced SEJTET termination technology was designed instead of the conventional PIOS isolation to obtain smaller chip area and protect HVICs from the occurrence of di/dt effect under PWM operation. Novel VDMOS/Resurf LDPMOS devices were developed compatibly to obtain the lowest , improve silicon utilization, and simplify key process steps.

1. Introduction

In recent years, many portable consumer electronic products have been sold on the market, such as 3G~4G iPhone mobile. Electroluminescent lamps (EL) technology is widely used as the display application of liquid crystal and backlighting because of the physical thinness and light uniformity, generating low power consumption for illumination lamp load with capacitance structure, especially lower cost than that of LED products recently [1, 2].

The EL load is essentially a capacitor structure with phosphor sandwiched between the electrodes. Recently EL driver integrated with full-bridge stage has been mostly developed on thin HV-BCD SOI material because it can play an important role in withstanding high breakdown voltage and protect the cross-talk effect from the noise through the current path of silicon substrate, employing buried oxide with relative dielectric constant () and shallow isolation from HV block and LV block. In general, high breakdown devices based on thin SOI are almost LDMOS with RESURF principle, rather than VDMOS [3]. However, the specific on resistance () of the former is larger than that of the later due to large curvature radius of potential distribution. On the other hand, with rich color for humanity display, the large number EL capacitance loads need to be driven, which requires that device size and the cost increase proportionally once HV-BCD SOI technology is still preferable. Therefore, it is paramount to find out a standard technology for EL driver to reduce the whole cost. Silicon epitaxial BCD technology is a popular technology applied in Plasma Display Panel (PDP) display products [4, 5], but several aspects of isolation and HV block integration are not effectively solved. For conventional p-isolation, not only there exists self-doping effect to degrade seriously the performance of the device and circuit, but also p-isolation structure with large area brings about a lot of defects to reduce the yield of HVICs products during long-time thermal cycle [6]. In addition, the process steps for VDNMOS and LDPMOS are complicated is revised as and isn’t easily compatible between two devices. Deep trench structure without cylindrical and spherical junctions is one of the candidates for edge termination design of future high voltage power devices to reduce the chip area and improve the block voltage [710], but sacrifical oxidation is always employed to remove the damage induced by dry etch so that widening the trench not only brings about the difficulty for refilling trench but also reduces seriously the integration level of HVICs. In this paper, an advanced wet-etch solution to remove the damage of developed SEJTET is firstly put forward. An 8-channel EL driver with the SEJTET in place of conventional p-isolation, a novel VDNMOS shared with the key process of RESURF LDPMOS, also has been developed on low cost bulk silicon to further save energy with higher efficiency and improve the integration level.

2. HV-BCD Process and Device Development

Figure 1 shows the cross-section view of advanced BCD process platform originated from the 0.35 um standard CMOS-process technologies. The whole processes were 21 steps and the p-drift step was shared by VDNMOS and LDPMOS for RESURF principle. The process platform provides the following devices isolated by SEJTET, including LVN/PMOS (: ) for digital analogical application, MVN/PMOS (: ) as buffer stages to drive the gate of HV device, and VDNMOS/LDPMOS (: ).

Figure 1: Cross-section view of HV-BCD process platform.

The deep trench with the space and depth of 2 um and 16 um is firstly etched by different RF power parameters of inductively coupled plasma (ICP) to obtain the vertical sidewall and rounded corners of trench and to avoid the convergence of the electric field, especially at the bottom. The wet-etch process is employed in place of conventional scarified oxidation to remove easily the silicon damage caused by high-energy-ion bombardment while maintaining the original space of trench during the trench-etch step. It is controlled about 15 seconds to uniformly remove the damages without spreading toward bulk silicon by the mixture of HF :  :  solution, the ultrasonicator under the frequency of 40 kHz and room temperature. Boron is implanted at large tilt angle of 30° around the trench at doses about  cm−2 and energies of 35~40 keV to form vertical junction termination extension. A 0.35 um thermal oxide liner is grown as the dielectric layer of trench and the process also plays an role in driving the implanted boron atoms. Finally, following refilling polysilicon and planarization processes for better shape and coverage, the trench is completed and connected with p-type substrate without long-time thermal cycle of PISO process.

Figure 2 shows SEM micrograph of SEJTET, PISO, and NSINKER. The sidewalls of SEJTET are smooth and slightly tapered, with an angle of ~87°. On the other hand, the 2 um space of SEJTET is much narrower than that of PISO with 20 um to block the same reverse voltage. So the HVICs die can be integrated with high-density level.

Figure 2: SEM micrograph of SEJTET, PISO, and NSINKER testing structure.

3. Results and Discussion

It is shown in Figure 3 that the BV characteristics of SEJTET have lower leakage current and almost 20 V higher than that of PISO. Figure 4 makes a comparison between the distribution of electrical field of SEJTET and that of trench by oxide refiller, employed by ISE-TCAD simulator. The former in Figure 4(a) is completely around the whole trench due to the polysilicon refiller layer into trench as floating electrode and the breakdown voltage is sustained by the implanted junction termination and grown oxide layer together. However, the distribution of electrical field in Figure 4(b) is two-dimensional and finally converges near the outer wall of the trench. So it is demonstrated that the electrical field of SEJTET appears uniformly and the breakdown voltage is higher.

Figure 3: Breakdown voltage characteristics of PISO and SEJTET structure.
Figure 4: The distribution of electrical field of (a) SEJTET and (b) the trench with oxide refiller.

Figure 5 shows the electrical characteristics of VDNMOS device. The threshold voltage () and the forward current of the device are 1.35 V and 26 mA, respectively. The specific on-resistance of the device, , is the lowest by comparison with those other studies reported [46]. To obtain the perfect figure of merit (), the merged poly-Si gate was designed and composed of the enhancement channel with the thin gate oxide and the depletion channel with the field oxide to reduce the gate charge , especially induced by the miller capacitances . In addition, the optimized high-energy phosphor implantation through the field oxide of depletion channel is employed to reduce on-resistance near JFET region. Finally, the VDNMOS device is double RESURF structure coshared with PDRIFT process parameter of RESURF LDPMOS to achieve low cost.

Figure 5: - characteristics of the VDNMOS (120 um) with different voltage (start/stop/step: 0 V/5 V/1 V).

For RESURF LDPMOS device, the threshold voltage () and the forward current of the device are −20 V and 3.5 mA, respectively. The gate oxide of the LDPMOS is grown together with the field oxide as the high side driver at full-bridge stage of HVICs.

Figure 6 shows the schematic circuit block of EL driver IC with 8 channels. The EL driver IC is in fact a full-bridge circuit. The high voltage level block can play a role in transforming high voltage power supply into the control signal to drive the full-bridge buffer. To improve the driving capacity, the VDNMOS with the width of 240 um is employed. The SEJTET structure is applied as parasitic NPN with shorted BC junction to sustain di/dt effect.

Figure 6: Schematic circuit block of EL driver IC.

The switch signal with pulse width modulation (PWM), rather than the sine wave, is employed to improve the efficiency. Figure 7 shows the switching waveforms of 100 V rating EL driver ICs during the operation of 400 Hz frequency. Two signals of the opposite phase are biased at two nodes of EL0 () to lighten the load. The rise and fall edge of switching waveforms is about 145 ns and 25 ns and it indicates that the switching power loss is small. On the other hand, the node, or connected with the drain of VDNMOS, is biased at high voltage. However, if is dropped from 100 V to zero at high frequency, will be about −0.7 V at freewheel time, which can be measured by voltmeter. So the parasitic PN junction of N-Epi/P-substrate turns on and a large number of minority-carrier injection charges are stored near the junction. When and are into normal operation, the reverse recovery current, , which is the same order of VDNMOS’ forward current, is extracted at short time under the bias of voltage and the VDNMOS is destroyed due to the effect of di/dt. SEJTET is in fact short BC junction of parasitic BJT transistor to extract the stored minority injection near the junction of N-Epi/P-substrate. The measurement of Emission Microscopes (EMMI) further demonstrated that there are no emission spots at full-bridge stage of HVICs [11].

Figure 7: The switching waveforms of 100 V rating EL driver ICs.

4. Conclusion

In summary, a 150 V rating EL driver IC is fabricated based on the standard 0.35 um CMOS technology. The proposed EL driver ICs integrate SEJTET, the novel VDNMOS, RESURF LDPMOS, and full-bridge stages. The experimental results show that the performances of the HV devices and the EL driver IC are good, and the cost makes the consumer satisfied due to cheaper bulk silicon technology than SOI technology.

Conflict of Interests

The authors declare that there is no conflict of interests regarding the publication of this article.


The authors thank all engineers at CETC58 for the whole development and fabrication of this project. The project was supported by the National Natural Science Foundation of China (Grant no. 61274077), the Guangxi Natural Science Foundation (Grant no. 2013GXNSFGA019003), the Jiangsu Natural Science Foundation (Grant no. BK2011173), the Guangxi Department of Education Project (no. 201202ZD041), the Guilin City Technology Bureau (nos. 20120104-8 and 20130107-4), and China Postdoctoral Science Foundation Funded Project (nos. 2012M521127 and 2013T60566).


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