III–V Nanowires: Synthesis, Property Manipulations, and Device Applications
Figure 10
Application of the metal decoration method in transforming printed NW parallel array devices into E-mode and in the fabrication of NMOS inverters composed of an E-mode and D-mode NWFETs. (a) SEM image and schematic illustration of an Au-cluster-decorated InAs NW array FET. (b) curves before and after decoration (decoration: Au clusters with an equivalent film thickness of 1.0 nm covered with a 20 nm thick evaporated Al2O3 layer; V). (c) Field-effect mobility of an InAs NW array FET before and after decoration ( V). (d) The voltage transfer characteristics (red) and the corresponding gain (black) of the representative NMOS inverter, the inset is the schematic circuit diagram of the inverter. Reproduced from [39] with permission from WILEY-VCH Verlag GmbH and Co. KGaA.
