Performance Evaluation of 14 nm FinFET-Based 6T SRAM Cell Functionality for DC and Transient Circuit Analysis
As the technology node size decreases, the number of static random-access memory (SRAM) cells on a single word line increases. The coupling capacitance will increase with the increase of the load of word line, which reduces the performance of SRAM, more obvious in the SRAM signal delay and the SRAM power usage. The main purpose of this study is to investigate the stability and evaluate the power consumption of a 14 nm gate length FinFET-based 6T SRAM cell functionality for direct current (DC) and transient circuit analysis, namely, in resistor-capacitor (RC) delay. In particular, Berkeley Short-channel IGFET Model-Common Multigate (BSIM-CMG) model is utilized. The simulation of the SRAM model is carried out in HSPICE based on 14 nm process technology. A shorted-gate (SG) mode FinFET is modeled on a silicon on insulator (SOI) substrate. It is tested in terms of functionality and stability. Then, a functional SRAM is simulated with 5 GHz square wave at the input of word line (WL). Ideal square wave and square wave with 100 RC, 5 RC, 1 RC, and 0.5 RC are asserted to the WL and the bit lines (BL&BLB) of SRAM. Voltage at node and is observed. The simulation shows that 1 RC is the minimum square wave that will store correct value in node and node . Thus, this discovery from the research can be used as a modeling platform for circuit designers to explore and improve the SRAM tolerance against RC delay.
Static random-access memory (SRAM) constitutes a large percentage of cell area in system on chip (SOC) designs due to high number of transistors for a single SRAM cell . Thus, SRAM cell typically utilizes minimum size transistor in order to realize higher density . Metal-oxide-semiconductor field-effect-transistor (MOSFET) technology scaling has been used to reduce size of SRAM cell over the past three decades . With the reduction of gate length that resulted in smaller SRAM cell, more SRAM cell can be allocated on the die without increasing the footprint, thus, increasing the memory storage capacity. Besides, MOSFET downscaling improves SRAM performance with higher transistor switching speed and reduces power consumption . However, as the technology scaled beyond 32 nm, conventional planar MOSFETs start to fail due to the threshold voltage () variation and short channel effect (SCE) . FinFET has been proven to be a better alternative for conventional nanoscale MOSFET when technology process is being scaled down below particularly at 32 nm node [5, 6]. FinFET offers several merits over MOSFET. For one, FinFET has better control over the channel due to several gates acting on the channel . Because of this, FinFET has excellent electrostatic properties . Besides, the FinFET’s excellent gate control over the channel reduces the source-drain leakage current and suppresses the SCE. Thus, further scaling down of a FinFET is possible. Moreover, FinFET’s lightly doped channel reduces random dopant fluctuation and effectively reduces the variation . The suppressed SCE and the enhanced gate control over channel allow the use of thicker gate oxide and, therefore, significantly reduce the gate oxide leakage current .
The 14 nm gate length FinFET is used as target because it will be used in the next generation of product by semiconductor manufacturing processes in a wide range of applications, namely, SRAM in this case. With each advancement in technology nodes, more SRAM cells can be positioned within a single word line (WL). For a design with many loads on a long wire, coupling capacitance can become a large factor in SRAM cell performance, namely, the rising transition of the word line and the falling transition of the local precharge signal . The coupling capacitance and the resistance of WL wire introduce resistor-capacitor (RC) relay at the input signal of the WL. Besides, the wire interconnect scaling introduces a nonscaling RC, which is intolerable for a high-performance SRAM design . The parasitic RC reduces the SRAM performance . As a result, SRAM’s RC and coupling delay correction circuit is being implemented to overcome the performance degradation . Nevertheless, there has not been any work on the consequences of RC delay on SRAM output signal. It is not demonstrated how much RC delay a SRAM cell can tolerate before its functionality fails. For the first time, the FinFET-based 6T SRAM internal nodes behavior is examined by using an array of square wave input of various RC delays and the minimum RC of a functional SRAM cell is acquired.
In this paper, the stability and power evaluation of a FinFET-based 6T SRAM cell in SPICE-direct current (DC) and transient analysis are explored. Voltage transfer characteristic (VTC) of the SRAM is revealed by analyzing the SRAM retention, SRAM read, and SRAM write operation. In addition, the static noise margin (SNM) is obtained for SRAM in retention mode, access mode, and write operation. Once the SRAM is stable, transient analysis is performed in HSPICE. Following that, the RC delay is introduced to WL signal, and the value of RC delay of the input signal that causes incorrect SRAM stored node value is obtained.
2. FinFET Device Parameter
The FinFET standard model is based on the Berkeley’s Berkeley Short-channel IGFET Model-Common Multigate (BSIM-CMG) SPICE library. The compact model library can be used for common multigate FETs. The FinFET default parameter is listed in the technical manual along with the Verilog-A sample model. In this exploration, a few of the parameters are modified whereas the other parameters are set as default value. The modified parameters are shown in Table 1.
In the simulation, 14 nm technology process parameters are utilized. Quantized width, which is similar to the width of a MOSFET, is utilized. Higher fins per finger means bigger width, hence stronger current flow. The equivalence width of a FinFET with single fin is the height and thickness of silicon fin that has contact with the gate. Therefore, the equivalence width of a FinFET with fins is , where is fin height, while is fin thickness. The default values of and are 30 nm and 15 nm, respectively. Thus, the equivalence widths of M1, M2, M3, M4, M5, and M6 are 300 nm, 150 nm, 300 nm, 150 nm, 150 nm, and 150 nm, respectively.
ratio is the write stability, while ratio is the read stability. The access transistor and the inverter’s p-FinFET have 2 fins per finger and the inverter’s n-FinFET has 4 fins per finger. The and ratios are, therefore, 1 and 2, respectively, and are sufficient such that read disturb and write fail will not occur . The voltage in this simulation is 1 V.
3. Inverter Model
SRAM consists of 2 inverters feeding each other in a closed loop. To analyze gain, noise margin, and power dissipation, single inverter is analyzed. Analysis of single inverter will reflect SRAM performance. Figure 1 shows the schematic for DC analysis on SRAM’s inverter. DC analysis is performed at node , and voltage of node is observed.
4. SRAM Model
A SRAM cell is constructed in HSPICE based on BSIM-CMG model card. Figure 2 shows the schematic of the SRAM cell model. is word line voltage,is bit line bar voltage, and is bit line voltage, while and are SRAM internal nodes that store 1 bit. Since the is 1 V, logic 1 means the voltage at node is 1 V, whereas logic 0 means voltage at node is 0 V. To read SRAM internal nodes value, both and are set to high. M5 and M6 are n-FinFET and are the access transistors, which serves to control the access to the SRAM internal storage during read operation and write operation. M5 and M6 will be turned on if WL is asserted. M1 and M3 are inverter’s n-FinFET, while M2 and M4 are inverter’s p-FinFET. Note that M4 and M3 are an inverter, M2 and M1 are another inverter. If WL is not asserted, the data in the SRAM cell is kept to a stable state, latching within the flip-flop formed by M1, M2, M3, and M4.
SRAM is analyzed in terms of DC analysis and transient analysis. DC analysis of SRAM involves investigation of SRAM stability using butterfly curve. The SNM is obtained graphically, which is the side length of the maximum square that can fit inside the butterfly curve. Transient analysis of SRAM involves investigation of SRAM behavior in real time. Square wave with RC is introduced to the word line of SRAM and the changes of behavior in SRAM internal nodes is observed.
5. RC Model
After the SRAM cell is proved to be stable, square waves with 100 RC, 5 RC, 1 RC, and 0.5 RC are applied to the word line. The square wave with RC is modeled by using a resistor and a capacitor as shown in Figure 3. is the input of perfect square wave, while is the square wave with RC that will be connected to WL. The input of the word line is a 5 GHz square wave. Thus, the half cycle time of the square wave is 100 ps. Table 2 shows the resistor and the capacitor value that are used to obtain different set of RC delay. A formula to calculate time constant, , is given by
6. SNM Extraction
To obtain the SNM graphically, a butterfly curve is first plotted. For the measurement of the butterfly curve, the feedback of the cross-coupled inverter is separated. Then, DC analysis is performed at node and node . The result of DC analysis is illustrated in Figure 7. Butterfly curve is obtained by toggling the and axis of one of the VTC curves, and merging the two separate VTC plots together. Figures 4 and 5 show the schematic for butterfly curve measurement of SRAM in retention mode and access mode, respectively. In those figures, note that that dotted lines are not wired as originally depicted in Figure 2. Figure 6 shows the VTC measurement of SRAM in write operation. The write operation is a process of writing logic 0 to and logic 1 to where BL is grounded and BLB is connected to .
7. Results and Discussion
Figure 7 shows the voltage transfer characteristic (VTC) of the SRAM’s inverter. The pink curve is the current measured at , while the green curve depicts the voltage at node . Note that the current in Figure 7 is in negative for the current measurement of a p-FinFET. is denoted as and vice versa.
The peak current (pointing downward) is at the point where gain of is highest, that is, at . This is due to short circuit leakage current, where input signal causes a direct current path between and GND for a short period of time during switching. Thus, power dissipation is highest at this point.
By using HSPICE .measure syntax and .op syntax, the average power dissipation and static power dissipation are obtained at 12.51 mW and 2.80 mW, respectively. Thus, the dynamic power, 9.71 mW, is given by subtracting the static power dissipation from the average power dissipation. The high static power dissipation indicate weak gate control over channel as the distance between source and drain is smaller and is an issue to be tackled.
Figure 8 shows the SRAM’s inverter gain (slope) and noise margin where the inverter switching threshold, noise margin, and gain of the inverter are measured. Inverter switching threshold, () is the intersection of VTC curve with the linear curve of . From Figure 8, is calculated at 0.37 V. is not centered at 0.5 V, but slightly to the left. This indicated a strong n-FinFET and a weak p-FinFET configuration. This is an expected condition for any SRAM with acceptable and ratio.
Noise margin is the performance metric of an inverter of how much it can tolerate noise or unwanted signal. Input low voltage, , and input high voltage, , are obtained when the slope of the VTC curve is −1. Any voltage lower than will be logic 0, whereas any voltage higher than will be logic 1. From Figure 8, is 0.19 V and is 0.43 V. Thus, the noise margin high (NMH) is given as , while noise margin low (NML) is given as . A high gain is desired for fast switching speed (low delay) and low leakage current. The gain of the inverter is calculated to be 7.60 from the intersection of VTC at .
Figures 9, 10, and 11 show the butterfly curve of SRAM in retention mode, access mode, and write operation, respectively. SNM is obtained graphically from the butterfly curve. The SNM of SRAM in retention mode and access mode are 0.24 V and 0.12 V, respectively. Endo et al.  obtained SNM of 0.19 V for SRAM in retention mode with 0.3 V and 0.36 V gate voltage on independent-gate (IG) mode FinFET. In our work, the SNM of a SRAM in write operation is at 0.38 V. This value is consistent with the findings of Endo et al.  where they obtained SNM of 0.35 V for SRAM in write operation. Higher SNM is expected for SG-FinFET .
Once SRAM cell is stable, a transient analysis is performed in HSPICE. Figure 12 shows the SRAM transient analysis over 800 ps, with input of an ideal square wave voltage without any RC delay. However, in the nonideal case, RC delay builds up at the input voltage of WL and affects the overall SRAM performance.
Four operations are performed during the 800 ps cycle. Each operation is executed when WL is asserted, which is at the increment of at 100 ps, 300 ps, 500 ps, and 700 ps. At 0 ps to 100 ps, node is initialized to logic 1. The data in SRAM cell held in latch. At the first assertion of WL, zero is written into SRAM cell. To store logic 0 into the SRAM cell, is set to zero. Correct sizing of SRAM ensures the data in latch is overwritten. At the second assertion of WL, a read operation is performed. During the read operation, both bit lines are precharged to a logical 1, and, then, WL is asserted. At the third assertion of WL, one is written into SRAM cell, and, at the forth assertion of WL, a read operation is performed.
Figure 13 shows the extraction of the top inverters from Figure 2. The slight increment of voltage at node from 300 ps to 400 ps and at node from 700 ps to 800 ps is due to pull up by through the access transistors, which are M5 and M6 in Figure 2. From 300 ps to 400 ps, is 1 V. Therefore, M4 is cut-off and it is not shown in Figure 13. On the other hand, M3 and M6 are active. They can be rearranged in simpler vertical form.
The transistor sizing of M3 is larger than that of a M6 due to a high ratio, thus, giving M3 a lower resistance compared to M6. Based on the voltage divider rule, node yields a lower voltage. As long as the width of M3 > M6, node will not be higher than 0.5 V when = 1 V. This is important to avoid the transistor from inverting and causing a read disturb.
Figure 14 illustrates the periodic wave input with different RC delay. By definition, 5 RC is the minimum RC that will complete the charge and the discharge process, producing full rail-to-rail swing. The square wave input is applied to word line, and the transient analysis in Figure 8 is performed to yield the output shown in Figure 15.
Figure 15 depicts the SRAM transient analysis within 800 ps for periodic wave input of 100 RC, 5 RC, 1 RC, and 0.5 RC word line voltages. The result in Figure 15 is separated into 8 sections and is analyzed separately. In Section 1, the SRAM cell is initialized to store 1. In Section 2, WL is asserted, and the SRAM internal nodes are influenced by and . For with 100 RC, drops to 0 instantaneously. For with lower RC, node voltage drop is more gradual.
decreases in Section 3 and the peak voltage is obtained at the end of Section 2 at 200 ps. At 200 ps, of 0.5 RC peaks at 0.4 V, and it is less than , which is 0.43 V from Figure 8. It is still not considered as logical 1. Thus, the drain current through access transistor is not strong enough to flip the signal at nodes and . As a result, the SRAM is unable to store 0 at 200 ps. In Section 3, of 0.5 RC is decreasing, and the signal at node is gradually stabilizing at 1. Nevertheless, note that SRAM is storing the incorrect value for of 0.5 RC at and . In Section 4, SRAM is in read operation. of 0.5 RC increases from 0.3 V to 0.5 V, but since both and are high, and remain unchanged and incorrect values are read. In Section 5, of 0.5 RC slowly decay and node is unchanged. In Section 6, 1 is written into SRAM cell. For of 100 RC, 5 RC, and 1 RC, the write operation is successful, with noticeable and longer delay for lower RC. Nevertheless, the voltage at node linger at 1 for of 0.5 RC. In Section 7, the SRAM internal nodes are consistent for all . In Section 8, SRAM is in read operation and no significant change is observed for the SRAM internal nodes.
Table 3 shows the comparison of time delay, average power, power-delay product (PDP), and energy-delay product (EDP) for different RC input square wave at SRAM’s word line. Both performance and power consumption deteriorate with RC delay. As such, square wave with a high RC delay is desirable to improve performance and reduce power consumption.
FinFET is a promising substitute for MOSFET to remove the challenge and obstacle faced by conventional MOSFET beyond 32 nm technology nodes. The use of FinFET has enabled further scaling of SRAM due to steeper subthreshold slope, reduced random dopant fluctuation, and relief of high-K material as gate oxide. However, as technology node decreases, parasitic RC is an issue to be concerned in SRAM design due to SRAM coupling capacitance and wire scaling. RC delay is an undesired yet unavoidable problem. From this work on 14 nm FinFET, it is revealed that 1 RC is the maximum tolerance for a SRAM cell to function correctly based on the SRAM metric performance for a wide range of various RCs, namely, time delay, average power, PDP, and EDP. This discovery can serve as a reference for SRAM circuit designers to understand the consequences in terms of RC delay when they are scaling down the SRAM cell. Circuit testers can benefit from the simulation results by comparing the simulation result with their device under test (DUT) to observe the severity of RC delay.
Conflict of Interests
The authors declare that there is no conflict of interests regarding the publication of this paper.
The authors would like to thank the Research Management Centre (RMC) of Universiti Teknologi Malaysia (UTM) for providing a tremendous support conduciveness to the research environment needed to complete project of this magnitude with personnel of far-reaching background. The authors would like to acknowledge the financial support from UTM GUP Research Grant (Vote nos. Q.J130000.2523.05H64 and Q.J130000.2523.05H59) and Fundamental Research Grant Scheme (FRGS) (Vote nos. R.J130000.7823.4F247 and R.J130000.7823.4F314) of the Ministry of Higher Education (MOHE), Malaysia.
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