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Journal of Nanomaterials
Volume 2014, Article ID 820763, 8 pages
http://dx.doi.org/10.1155/2014/820763
Research Article

Performance Evaluation of 14 nm FinFET-Based 6T SRAM Cell Functionality for DC and Transient Circuit Analysis

Faculty of Electrical Engineering, Universiti Teknologi Malaysia (UTM), 81310 Skudai, Johor, Malaysia

Received 15 February 2014; Revised 28 June 2014; Accepted 6 July 2014; Published 23 July 2014

Academic Editor: Shiren Wang

Copyright © 2014 Wei Lim et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. A. S. Pavlov, Design and test of embedded SRAMs [Ph.D. thesis], University of Waterloo, Waterloo, Canada, 2005.
  2. V. Sharma, SRAM Bit Cell Optimization, Springer Science, Business Media, New York, NY, USA, 2013.
  3. H. Iwai, “Roadmap for 22 nm and beyond (invited paper),” Microelectronic Engineering, vol. 86, no. 7-9, pp. 1520–1528, 2009. View at Publisher · View at Google Scholar · View at Scopus
  4. H. Kawasaki, V. S. Basker, T. Yamashita et al., “Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond,” in Proceedings of the International Electron Devices Meeting (IEDM '09), pp. 1–4, December 2009. View at Publisher · View at Google Scholar · View at Scopus
  5. F. Wang, Y. Xie, K. Bernstein, and Y. Luo, “Dependability analysis of nano-scale FinFET circuits,” in Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, pp. 399–404, Karlsruhe, Germany, March 2006. View at Publisher · View at Google Scholar · View at Scopus
  6. B. Swahn and S. Hassoun, “Gate sizing: FinFETs vs 32nm bulk MOSFETs,” in Proceedings of the 43rd Design Automation Conference, pp. 528–531, 2006.
  7. T. Poiroux, M. Vinet, O. Faynot et al., “Multiple gate devices: advantages and challenges,” Microelectronic Engineering, vol. 80, pp. 378–385, 2005. View at Publisher · View at Google Scholar · View at Scopus
  8. R. Jatooth, M. Veshala, and K. R. Reddy, “Reduction of short-channel effects in FinFET,” International Journal of Engineering and Innovative Technology, vol. 2, no. 9, 2013. View at Google Scholar
  9. A. B. S. Y. Kobayashi, K. Tsutsui, K. Kakushima, P. Ahmet, V. R. Rao, and H. Iwai, “Analysis of threshold voltage variations of FinFETs relating to short channel effects,” ECS Transactions, vol. 16, no. 40, pp. 23–27, 2009. View at Publisher · View at Google Scholar
  10. S. A. Tawfik, Z. Y. Liu, and V. Kursun, “Independent-gate and tied-gate FinFET SRAM circuits: design guidelines for reduced area and enhanced stability,” in Proceedings of the International Conference on Microelectronics, pp. 370–373, 2007.
  11. D. G. Behrends, T. A. Christensen, T. R. Hebig, M. Launsbach, and D. M. Nelson, “Implementing rc and coupling delay correction for sram,” USA Patent, 2013.
  12. J. Warnock, “Circuit and PD challenges at the 14 nm technology node,” in Proceedings of the ACM International Symposium on Physical Design (ISPD '13), pp. 66–67, March 2013. View at Publisher · View at Google Scholar · View at Scopus
  13. F. Nemati and J. D. Plummer, “Novel thyristor-based SRAM cell (T-RAM) for high-speed, low-voltage, giga-scale memories,” in Proceedings of the IEEE International Devices Meeting, Technical Digest (IEDM '99), pp. 283–286, Washington, DC, USA, December 1999. View at Scopus
  14. R. Ramesh, M. Madheswaran, and K. Kannan, “Optical effects on the characteristics of a nanoscale FinFET,” Progress In Electromagnetics Research B, no. 21, pp. 235–255, 2010. View at Google Scholar · View at Scopus
  15. R. D. Adams, High Performance Memory Testing: Design Principles, Fault Modeling and Self-Test, Springer, Boston, Mass, USA, 2003.
  16. K. Endo, S. O'Uchi, T. Matsukawa et al., “Enhancing SRAM performance by advanced FinFET device and circuit technology collaboration for 14nm node and beyond,” in Proceedings of the Symposium on VLSI Technology Digest of Technical Papers (VLSIT '13), pp. T214–T215, June 2013. View at Scopus
  17. A. Muttreja, N. Agarwal, and N. K. Jha, “CMOS logic design with independent-gate FinFETs,” in Proceedings of the 25th IEEE International Conference on Computer Design (ICCD ’07), vol. 1, pp. 560–567, Lake Tahoe, Calif, USA, October 2007. View at Publisher · View at Google Scholar · View at Scopus