Characteristics of a Multiple-Layered Graphene Oxide Memory Thin Film Transistor with Gold Nanoparticle Embedded as Charging Elements

Figure 2

(a) Schematics for the fabrication of the-rGO based devices. (A) Rinsing the SiO₂ coated Si wafer. (B) Dipping the substrate into the APTES solution. (C) Dip-coating the substrate into the Au NP solution and in the GO solution and then reducing under H₂N₄ vapor. (D) Dip-coating the substrate into the GO solution and then reducing under H₂N₄ vapor. (E–G) Depositing the Au/Cr electrode on the rGO devices. (b) TEM image of rGO-memory device (scale bar: 5 nm) with inset graphs of Raman (left) and XPS (right) spectra of the rGO.

(a)

(b)