Journal of Nanotechnology / 2012 / Article / Fig 11

Review Article

Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications

Figure 11

(a) Process integration flow of vertical SiNW junction-based NC-Flash: (a-1) vertical SiNW formation; (a-2) As is implanted to form the source; (a-3) gate stack deposition (O-N-O or O-NC-O for SONOS and NC-flash, resp.) and gate pad definition; (a-4) tip poly and O-NC-O removal, followed by drain implant; (a-5) metallization; (b) process integration flow of vertical JL-SONOS: (b-1) bulk implant and annealing; (b-2) vertical SiNW formation; (b-3) gate stack deposition and gate pad definition; (b-4) tip poly and ONO removal; (b-5) metallization; (c) tilted top view SEM image of SONOS/JL-SONOS fabrication during key process steps (left to right): vertical SiNW formation; gate pad definition; tip poly and ONO removal; metallization. (Reprinted with permission from [45]. [2011] IEEE.)
492121.fig.0011

Article of the Year Award: Outstanding research contributions of 2020, as selected by our Chief Editors. Read the winning articles.