Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications

Figure 14

(a) Programming and (b) erasing characteristics using FN tunneling of vertical SiNW-based GAA JL-SONOS memory device with channel doping of 1 × 10¹⁷ cm⁻³ and 1 × 10¹⁹ cm⁻³. (Reprinted with permission from [45]. [2011] IEEE.)

(a)

(b)