Journal of Nanotechnology / 2012 / Article / Fig 15

Review Article

Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications

Figure 15

Multibit programming characteristics of JL-SONOS memory with a gate biases of 12, 14, and 16 V for 1 ms. Wire diameter = 20 nm, channel doping = 1 × 1 0 1 9 /cm−3. (Reprinted with permission from [45]. [2011] IEEE.)
492121.fig.0015

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