Journal of Nanotechnology / 2012 / Article / Fig 2

Review Article

Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications

Figure 2

(a) Single silicon nanowire with bottom isolation, (b) after gate stack deposition, (c) after gate extension pad definition and HDP oxide deposition followed by etch back defining gate length, (d) after poly-silicon end cap removal, (e) removal of oxide followed by S/D and gate implant (single implant for all three electrodes), (f) final device after metalization. (Reprinted with permission from [15]. [2008] IEEE.)
492121.fig.002a
(a)
492121.fig.002b
(b)
492121.fig.002c
(c)
492121.fig.002d
(d)
492121.fig.002e
(e)
492121.fig.002f
(f)

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