Journal of Nanotechnology / 2012 / Article / Fig 24

Review Article

Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications

Figure 24

(a) Snapshot of the completed TEG (6 pads at the sides of the TEG to allow connections of different areas). Connecting the terminals 1 and 5 establishes an ohmic path between several serpentine P- and N-elements in a 5 mm × 5 mm area. (b) Different layers used in the experimental setup. Indicated in the different layers is the thermal resistance used in the calculations. The heat sink thermal resistance calculation is based on Al with a dimension of 5 cm × 5 cm × 5 mm. (Reprinted with permission from [70]. [2011] IEEE.)
492121.fig.0024a
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492121.fig.0024b
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