Journal of Nanotechnology / 2012 / Article / Fig 6

Review Article

Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications

Figure 6

(a) Band diagram of TFET showing tunneling junction, (b) 𝐼 𝑑 - 𝑉 𝑔 and characteristics of a vertical SiNW TFET with diameter 70 nm, gate length 200 nm and gate oxide thickness 4.5 nm. (Reprinted with permission from [28]. [2009] IEEE.)
492121.fig.006a
(a)
492121.fig.006b
(b)

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