Journal of Nanotechnology / 2012 / Article / Tab 1

Review Article

Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications

Table 1

Benchmarking of lateral and vertical nanowire devices with planar.

planarNW (lateral)NW (vertical)

Device circuit Areas ( ๐ด ) 8 ๐น 2 , 4 0 ๐น 2 8 ๐น 2 , 2 4 ๐น 2 Shrink ~40% 4 ๐น 2 , 1 2 ๐น 2 Shrink ~70%
Speed ๐›ผ 1 / ๐‘ก ๐›ผ
( ๐‘… ๐ถ ) โˆ’ 1 ๐›ผ ( ๐ด ) โˆ’ 3 / 2
1 โˆผ 2 . 2 ร— โˆผ 6 . 1 ร—
Power ๐›ผ โ€‰โ€‰ ๐ถ ๐‘‰ 2 ๐›ผ ( ๐ด ) 1 1 โˆผ 0 . 6 ร— โˆผ 0 . 3 ร—

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