Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications

Table 1

Benchmarking of lateral and vertical nanowire devices with planar.

	planar	NW (lateral)	NW (vertical)
Device circuit Areas (𝐴)	8𝐹^2, 40𝐹^2	8𝐹^2, 24𝐹^2 Shrink ~40%	4𝐹^2, 12𝐹^2 Shrink ~70%
Speed 𝛼 1/𝑡𝛼; (𝑅𝐶)^−1𝛼(𝐴)^−3/2	1	∼2.2×	∼6.1×
Power 𝛼  𝐶𝑉^2𝛼(𝐴)^1	1	∼0.6×	∼0.3×