Table of Contents Author Guidelines Submit a Manuscript
Journal of Sensors
Volume 2016, Article ID 7281031, 9 pages
http://dx.doi.org/10.1155/2016/7281031
Research Article

A Tile-Based EGPU with a Fused Universal Processing Engine and Graphics Coprocessor Cluster

1School of Information Science and Engineering, Shandong University, No. 27, South Shanda Road, Jinan 250100, China
2Shandong Provincial Key Laboratory of Network Based Intelligent Computing, University of Jinan, No. 336, West Nan Xinzhuang Road, Jinan 250022, China
3Administration Center, Shandong Academy of Information and Communication Technology, Jinan 250101, China

Received 16 March 2015; Revised 15 May 2015; Accepted 18 May 2015

Academic Editor: Gwanggil Jeon

Copyright © 2016 Yang Wang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. L. Garber, “GPUs go mobile,” Computer, vol. 46, no. 2, Article ID 6457381, pp. 16–19, 2013. View at Publisher · View at Google Scholar · View at Scopus
  2. Imagination Technologies, PowerVR MBX Technology Overview, Revision 1, Imagination Technologies, 2009.
  3. C. M. Wittenbrink, E. Kilgariff, and A. Prabhu, “Fermi GF100 GPU architecture,” IEEE Micro, vol. 31, no. 2, pp. 50–59, 2011. View at Publisher · View at Google Scholar · View at Scopus
  4. J. D. Owens, M. Houston, D. Luebke, S. Green, J. E. Stone, and J. C. Phillips, “GPU computing,” Proceedings of the IEEE, vol. 96, no. 5, pp. 879–899, 2008. View at Publisher · View at Google Scholar · View at Scopus
  5. S. W. Keckler, W. J. Dally, B. Khailany, M. Garland, and D. Glasco, “GPUs and the future of parallel computing,” IEEE Micro, vol. 31, no. 5, pp. 7–17, 2011. View at Publisher · View at Google Scholar · View at Scopus
  6. E. Lindholm, J. Nickolls, S. Oberman, and J. Montrym, “NVIDIA Tesla: a unified graphics and computing architecture,” IEEE Micro, vol. 28, no. 2, pp. 39–55, 2008. View at Publisher · View at Google Scholar · View at Scopus
  7. B.-G. Nam, H. Kim, and H.-J. Yoo, “A low-power unified arithmetic unit for programmable handheld 3-D graphics systems,” IEEE Journal of Solid-State Circuits, vol. 42, no. 8, pp. 1767–1778, 2007. View at Publisher · View at Google Scholar · View at Scopus
  8. Imagination Technologies, POWERVR Series5 Graphics SGX Architecture Guide for Developers, Version 1.0.8, Imagination Technologies, 2011.
  9. M. Pharr and R. Fernando, GPU Gems 2: Programming Techniques for High-Performance Graphics and General-Purpose Computation, Addison-Wesley, New York, NY, USA, 2005.
  10. H.-Y. Kim, Y.-J. Kim, J.-H. Oh, and L.-S. Kim, “A reconfigurable SIMT processor for mobile ray tracing with contention reduction in shared memory,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 4, pp. 938–950, 2013. View at Publisher · View at Google Scholar · View at Scopus
  11. C.-H. Yu, K. Chung, D. Kim, S.-H. Kim, and L.-S. Kim, “A 186-Mvertices/s 161-mW floating-point vertex processor with optimized datapath and vertex caches,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 10, pp. 1369–1382, 2009. View at Publisher · View at Google Scholar · View at Scopus
  12. J. H. Woo, J. H. Sohn, H. Kim, and H. J. Yoo, “A 195 mW/152 mW mobile multimedia SoC with fully programmable 3-D graphics and MPEG4/H.264/JPEG,” IEEE Journal of Solid-State Circuits, vol. 43, no. 9, pp. 2047–2056, 2008. View at Publisher · View at Google Scholar · View at Scopus
  13. J.-H. Sohn, J.-H. Woo, M.-W. Lee, H.-J. Kim, R. Woo, and H.-J. Yoo, “A 155-mW 50-m vertices/s graphics processor with fixed-point programmable vertex shader for mobile applications,” IEEE Journal of Solid-State Circuits, vol. 41, no. 5, pp. 1081–1091, 2006. View at Publisher · View at Google Scholar · View at Scopus
  14. Y.-J. Kim, H.-E. Kim, S.-H. Kim, J.-S. Park, S. Paek, and L.-S. Kim, “Homogeneous stream processors with embedded special function units for high-utilization programmable shaders,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 9, pp. 1691–1704, 2012. View at Publisher · View at Google Scholar · View at Scopus