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Research Article | Open Access

Volume 2021 |Article ID 6651642 | https://doi.org/10.1155/2021/6651642

Xiaowei Zhang, Wei Fan, Jianxiong Xi, Lenian He, "14-Bit Fully Differential SAR ADC with PGA Used in Readout Circuit of CMOS Image Sensor", Journal of Sensors, vol. 2021, Article ID 6651642, 17 pages, 2021. https://doi.org/10.1155/2021/6651642

14-Bit Fully Differential SAR ADC with PGA Used in Readout Circuit of CMOS Image Sensor

Academic Editor: Changhui Hu
Received13 Oct 2020
Revised23 Jan 2021
Accepted27 Jan 2021
Published23 Feb 2021

Abstract

This paper proposes a 14-bit fully differential Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with a programmable gain amplifier (PGA) used in the readout circuit of CMOS image sensor (CIS). SAR ADC adopts two-step scaled-reference voltages to realize 14-bit conversion, aimed at reducing the scale of capacitor array and avoiding using calibration to mitigate the impact of offset and mismatch. However, the reference voltage self-calibration algorithm is applied on the design to guarantee the precision of reference voltages, which affects the results of conversion. The three-way PGA provides three types of gains: 3x, 4x, and 6x, and samples at the same time to get three columns of pixel signal and increase the system speed. The pixel array of the mentioned CIS is , and the pixel pitch is . The prototype chip is fabricated in the 180 nm CMOS process, and both digital and analog voltages are 3.3 V. The total area of the chip is  mm2. At 150 kS/s sampling rate, the SNR of SAR ADC is 71.72 dB and the SFDR is 82.91 dB. What is more, the single SAR ADC consumes 477.2 uW with the 4.8 differential input signal and the total power consumption of the CIS is about 613 mW.

1. Introduction

An image sensor is a device that converts light signals into electrical signals. In recent years, the demand for an image sensor is continuously increasing, which is widely used in mobile phones, SLR digital cameras, automotive electronics, and security industry fields [1]. Mainstream image sensor technologies are roughly divided into two types: CCD image sensor and CMOS image sensor (CIS). With the advantages of high resolution and low noise, CIS gradually becomes the first choice of sophisticated and important fields. Readout circuit is the core part of CIS, whose continuous speed is normally between 50 fps and 10 Mfps while ADC is the important module in readout circuit [2, 3]. Based on the number of ADCs used in a circuit, column ADC may be the most suitable ADC applied in the large pixel array, keeping a good balance between area, power, and speed while the other types are chip ADC and pixel ADC. With the size of pixel array increasing, the mutual interference between signals will increase the complexity of the system when the pixel array studied in most researches is less than [46]. Combined with the above situation, SAR ADC is employed widely when the scale of pixel array increases. Compared with other types of ADC, the balance between power consumption and speed is always the advantage of SAR ADC. In order to maximize the dynamic range of SAR ADC, a programmable gain amplifier (PGA) is the necessary part used in weak-light conditions, though it usually consumes a substantial amount of power. The performance of SAR ADC and PGA directly affects the quality of the images captured by the image sensor while the bits of SAR ADC decide the resolution and the PGA determines the dynamic range.

The pixel array of CIS presented in this paper is , and the pixel size is , which is larger than normal CIS. In order to read signal as fast as possible, column readout circuit is adopted. The resolution of SAR ADC is 14 bits, which is relatively high. Usually, a calibration algorithm is adopted in this situation while the SAR ADC used in this paper do not follow the mainstream practice, considering the power, area, and complexity. However, a reference voltage precision optimization algorithm is used to improve the performance of SAR ADC. What is more, PGA provides the gain of 3x, 4x, and 6x, based on the input signal.

The initial shorter conference paper introduces the working principle and results of the CIS chip briefly [7]. Based on the initial paper, this paper is organized as follows, which shows more details of the CIS chip. Section 2 describes the architecture of the system. The operation principle of different modules is discussed in Section 3, including implementation details of ADC and PGA. The simulated and experimental results of the prototype are illustrated in Section 4. Section 5 concludes this paper.

2. System Architecture

Figure 1 shows the architecture of the proposed CIS, which includes pixel array, PGA, ADC, register, row scanner, reference generator, reference calibration, Low-Voltage Differential Signaling (LVDS) drivers, and auxiliary circuits. Considering more than one million pixels and the frame rate (50 fps), a column readout circuit is used when a row scanner is applied on selecting a specific row. When the row is determined by a row scanner, a column readout circuit begins to work. The small signal is amplified by PGA and then converted into a digital signal by ADC, which is shifted into register. Finally, the LVDS driver takes on the role of output signal. The proposed CIS works at the speed of 150 KS/s, and the reference clock signal is 2.7 MHz.

During the whole process, the function of PGA is to sample exposure signal, reset signal, and provide three gains: 3x, 4x, and 6x. Owing to exposure signal lower than reset signal, which means that the calculated signal for the difference between exposure signal and reset signal is single-ended, the fixed deviation is added to the system for converting a single-ended signal into differential forms, which is consistent with SAR ADC input. What is more, in order to speed the upsampling process, three-way PGA corresponding to three columns of pixel array is adopted instead of sampling signal one by one. The gain of PGA is decided by the size of signal, which should be distinguished before transferred into SAR ADC.

14-bit fully differential SAR ADC is necessary for the proposed CIS, which directly affects the image. The high-precision reference voltage is the guarantee of SAR ADC. As a result, a scaled reference generator is used with a reference calibration module.

The system timing of the proposed CIS is shown in Figure 2. The working cycle of the chip is 18 ADC_CLKs (reference clock signal). During the first 3 ADC_CLKs, a specific row is chosen when SAR ADC samples the signal amplified by PGA. The remained 15 ADC_CLKs mainly include the following work: the conversion of SAR ADC, the signal sampling of PGA, and the data reading. During the sampling process of PGA, the reset signal is sampled first and the exposure signal follows.

3. Operation Principle and Circuit Implementation

In this section, the operation principle and circuit implementation of CIS are introduced, which consist of PGA, SAR ADC, and reference voltage self-correction algorithm. Referring to SAR ADC, principle and timing are described. What is more, the core parts of SAR ADC are presented in detail, including comparator and DAC.

3.1. PGA

In the CMOS image sensor system, a pixel sensor which demonstrates the brightness of the outside light depends on the difference between reset signal and exposure signal. The form of reset and exposure signal is voltage, which needed to be sampled and amplified into a suitable size. In order to increase the speed of the readout circuit, reset and exposure signals are sampled by different capacitors and amplified by a differential amplifier.

Based on the principle of pixel array, the reset signal is always higher than the exposure signal, which results in the unipolar difference all the time. The proposed architecture of PGA shown in Figure 3 aims at solving the problem by introducing a fixed deviation. represents the reset and exposure signals, which is the output signal of the 5-T pixel sensor. With the help of a combination of capacitors , , , and , the unipolar difference between them is converted into bipolar form and averaged over the positive and negative half axes. The single-ended signal is transferred to a differential signal, which is more convenient for SAR ADC. The control action of switches and is the opposite, which decides the gain of PGA. The switching of and changes the magnitude of the gain from 3x to 4x or 6x. What is more, and are the reference voltage of SAR ADC, which is applied on PGA as well. The purpose of adopting different reference voltages is to generate the needed deviation.

The working cycle of PGA is 18 ADC_CLKs, which is the same as the system and ADC working cycle. The following analysis of operation principle of PGA is based on the charge. The change on charge represents the switch of working status.

As shown in Figure 4, reset signal which is called is got by PGA. During the first 7 ADCs, switches , , and are on while is off on the upper capacitor array part. What is more, switches and are on when the lower plates of capacitors and are connected to the ground and the lower plates of capacitors and are connected to the . The total charge stored in capacitors , , , and on the upper part is calculated as follows:

At the 8th ADC_CLK, all switches on the upper part begin to change. The switches and turn off while the switch turns on. What is more, turns off first and turns on again in the half of ADC_CLK. The lower plates of and are connected from to the ground. However, the capacitors are not connected to new power and the total charge keeps on. Considering the switch is open, the upper plate voltages of capacitors are not regular. Based on the charge conservation and the ignoration of offset, the voltage of the upper plate can be achieved by

The latter 7 ADC_CLKs are from 9 to 15 ADC_CLKs. In this period, the exposure signal is sampled by the lower part of a circuit. The principle and process of sampling are the same as the reset signal. At the beginning, the switches , , and are closed and is open. The charge sampled in this procedure is

And then, the switch turns on and , , and turn off. Finally, and keep off and and keep on, where the state of is from open to closed. Through this process, the following equations can be obtained:

Combining equations (1)–(6), the differential signal sent into the amplifier is described by the following equations:

According to equation (8), apart from the difference between and , the fixed deviation is introduced as expected, which realizes the goal of making the signal spread uniformly. After sampling is finished, switches and turn on, which lasts 3 ADC_CLK.

During the phase, the function of and is to choose different gains which is called amplify phase as well. The value of capacitors used in the PGA is shown in Table 1. The calculation formula of gain is




If switches and both turn on, the gain of PGA is 6x. While if one of them turns off, the gain of PGA is 4x. Once both are closed, the smallest gain 3x is achieved under this situation.

As a significant part of PGA, the operational amplifier needs to be paid enough attention to. Figure 5 shows the architecture of amplifier, which needs high gain, enough bandwidth, strong driving capability, and low noise. The proposed amplifier contains two stages: amplifying stage and driving stage, aimed at providing enough gain and increasing the ability of driving. Compared with other architectures of amplifier, the wider input common mode range and larger output swing are the advantages of folding cascode operational amplifier, which is applied in this situation and provides major gain. The cascode stage makes the increase, which leads to high gain.

The driving stage is the floating-biased class AB output stage, having a strong driving ability. The size of following-up capacitor arrays used in the SAR ADC is large, which puts forward higher requirements for the driver of the input stage. Considering the high power consumption of folding cascode amplifier, the floating biased transistors MN5, MN6, MP7, and MP8 are utilized to decrease and stabilize quiescent current of the output stage as analyzed in [8]. The overall gain of the two-stage amplifier is

When it comes to noise, the high noise is always the drawback of folding cascode amplifier, as depicted in [9]. However, the operational amplifier of this structure meets design requirements. In order to improve the performance of noise, PMOS is adopted as input, which is better than NMOS on noise. What is more, larger value of and smaller value of and are chosen to reduce the noise. Under the circumstance, the value of W/L needs to be weighed carefully, which is important for improving the SNR of SAR ADC.

3.2. SAR ADC

The most important module of CIS is SAR ADC, which is placed after PGA. The function of SAR ADC is to convert the analog signal amplified by PGA into the digital signal.

The sampling speed of SAR ADC required by the system is 150 KS/s, and the resolution of SAR ADC is 14 bits. Normally, the differential input method is selected to suppress the interference of common mode factors and the charge redistribution theory is applied on SAR ADC, which was first proposed by McCreary and Gray [10]. Combing the above two points, the architecture of double reference voltage SAR ADC is widely used. If the resolution of SAR ADC is beyond 10 bits, the capacitor array will be very large, taking up unexpected area in the situation. In order to avoid a huge capacitor array, the two-step scaled-reference SAR ADC is put forward, which is based on the charge redistribution theory as well. This structure was first proposed by South Korea’s Shin for CMOS image sensor applications [11]. Two-step scaled reference contains four reference voltages, and the increased reference voltage is to reduce the area of the capacitor array.

3.2.1. Principle and Timing

The architecture of the proposed SAR ADC is shown in Figure 6, containing DAC, comparator, and SAR Logic. Compared with double reference voltages, two-step scaled reference keeps on the size of capacitor array with the complex conversion process. Use the same size capacitor array, but the resolution has changed from the previous 7 bits to 14 bits, which is the core advantage of the architecture. On the other hand, the requirement of precision of reference voltage is increasing. The added reference voltages and need higher accuracy compared with and . and are the reference voltages used in the first stage while the and are applied on the second stage. The value of is

and are the output signals of PGA, which are the same as and shown in Figure 5. is the common voltage of the input signal of SAR ADC.

The whole process includes four parts: sampling, holding, comparison, and output. The architecture adopts lower plates of capacitors to sample. During the sampling phase, and are chosen by MUX when all upper plates of capacitors are connected to . The signal and are sampled by the capacitor array because all lower plates of capacitors are connected to and . The charge stored in all capacitors is calculated as

Converting the input voltage into the form of charge is the principle of sampling. In order to hold the sampled charge, the upper plates of capacitors do not connect to the . The lower plates of capacitors in the negative part are connected to the when the lower plates of capacitors in the positive part are connected to the . After finishing the procedure, according to the charge conservation theory, the following equations are obtained:

Combining equations (12)–(15), the input signal of comparator is achieved:

Once the holding phase is finished, SAR ADC enters the comparison phase, which contains two parts: high 7-bit conversion and low 7-bit conversion. The reference voltages of high 7-bit conversion are and while and are the reference voltages of low 7-bit conversion. Controlling the connection of lower plates of capacitor array to adjust the input signal of comparator and then get the corresponding code according to the comparison result is the core working principle of comparison.

During the high 7-bit conversion, the MSB () is taken for example and the others are the same working process. At the beginning, the lower plate of highest capacitance () in the positive side is connected from to and the lower plate of the highest capacitor () in the negative side is connected to . The other plates of capacitance keep on the current states. The change of charge stored in the capacitor array is calculated as follows:

The input signal of comparator follows with :

If the is negative, the result of comparator is 0, which means is larger than and the SAR Logic should control the switch to keep on. Otherwise, the result of comparator is 1. The lower plate of highest capacitance () in the positive side is connected to instead of , and the negative side is the opposite, which also represents which is smaller than . The rest 6 bits work in the same way.

The conversion of low 7 bits is different from high 7 bits. When the conversion of the 7th bit is finished, the lower plate of dummy capacitor in the negative side is connected to and the lower plates of other capacitors are connected to or , which are determined by the original state and increases by . The purpose of the switch action is to keep the value of on with the increasement of connected voltages of capacitors in the negative side and decrease of connected voltage of dummy capacitor. The decreased charge and can be expressed as

According to equations (21) and (22), and are equal, which means the value of does not change. At this time, the requirements of low 7-bit conversion are met. In order to explain the process, the comparison of 6th bit is taken for example. Because the low 7-bit conversion and high 7-bit conversion use the same capacitor array, the procedure is similar. What is more, the switch action of lower 7 bits is based on the high 7 bits. For instance, the conversion of 6th bit is related to 13th bit. If is 0, which means the lower plate of the highest capacitance () in the positive side is connected to and the lower plate of the highest capacitance () in the negative side is connected to , the connection voltage of lower plate of the highest capacitance () in the positive side will increase by and the connection voltage in the negative side will decrease by . The increased charge and increased voltage of input signal are achieved:

If is 1, which means the lower plate of the highest capacitance () in the positive side is connected to and the lower plate of the highest capacitance () in the negative side is connected to . The process is similar to the situation of . The change on charge and the input signal are the same as well. The result of comparison determines the switch actions, which has been explained above. The voltage represented by the capacitor array during the process is calculated:

The last six bits adopts the same working process. Combining the conversion of high 7 bits and low 7 bits, the analog signal sampled by PGA is converted into 14-bit digital code.

The timing diagram of SAR ADC is shown in Figure 7. The reference clock is still ADC_CLK. The whole procedure occupies 18 ADC_CLKs. The 3 ADC_CLKs are used for sampling while 14 ADC_CLKs are adopted for comparison and the function of the last ADC_CLK is to output the results. During the comparison, the comparator begins to compare at the rising edge of ADC_CLK and latch the signal at the following edge of ADC_CLK. After latching the last comparison, the signal DATA_Ready turns to a high level and keeps on before the first ADC_CLK finishes.

3.2.2. Comparator

The comparator almost decides the speed of SAR ADC. In order to speed up the comparison, the StrongARM Latch topology is used, which is explained in [12]. The StrongARM latch topology is not only good at speed but also expert in saving power. The circuit is shown in Figure 8.

The StrongARM latch is based on positive feedback, which includes two working stages: reset phase and regeneration phase. At the beginning, the CLK is low. NM1 and NM2 are off while Node1 and Node2 are connected together to keep the same voltage for resetting. The output and are reset to the power supply voltage by PM3 and PM4, respectively. What is more, PM1, PM2, NM4, and NM5 are off. When in the regeneration stage, CLK is high and the current flows through NM1 and NM2. Assuming that , the current flowing through NM1 is larger than NM2, causing the voltage of Node1 to drop faster than Node2. When the voltages of Node1 and Node2 arrive at , NM4 and NM5 turn on. Because Node1 first reaches , begins to drop, which also leads to the dropping speed of slow down. Positive feedback is formed and becomes finally. The loop gain of the positive feedback loop is

The voltage change of the whole process is shown in Figure 9.

In order to reduce the impact of input offset voltage and kickback noise, the preamplifier is adopted, the architecture of which is shown in Figure 10. The preamplifier uses Current Starving Technical [13] to increase the gain instead of using cascode structure. The small signal gain is calculated as follows:

represents the ratio coefficient of the current flowing through the NM4 or NM5, which determines the gain of amplifier. Aimed at making the resolution of latch shown in Figure 8 reach 0.5LSB, the gain of the amplifier requires at least

The gain is related to closely. Based on the requirement of resolution and process characteristics, the three-stage operational amplifier is adopted.

The amplifier itself owns offset voltage, requiring the gain of the input stage maximized. The input offset voltage of the last two stages can be ignored when it is equivalent to the input. However, the offset voltages are still needed to be eliminated as much as possible, which is depicted in Figure 11.

The work of amplifier contains two phases: reset phase and amplification phase. In the reset phase, both input terminals are short to the common mode voltage through the switch when the two output terminals are also short to the . The output offset is stored in capacitor and , which is the opposite to the input offset:

When the amplifier enters the amplification stage, the switches connected to do not keep on and input signals and connect to the input of amplifier. At this time, the output signal of amplifier can be obtained:

According to equation (30), the output does not contain , which means the effect of offset voltage is eliminated. The complete comparator design is shown in Figure 12, including amplifiers, latch, and RS flip-flop. The three-stage preamplifier amplifies the input signal, and then, the amplified signal is compared by StrongARM latch quickly. The function of RS flip-flop is to output the results to the logic register.

3.3. Reference Voltage Self-Calibration Algorithm

The proposed architecture adopts a two-step scaled reference. The resolution of two reference voltages and is up to , which is difficult for design. Once the accuracy of the reference voltage is far from the target value, the results of SAR ADC are greatly affected. The reference voltage self-calibration algorithm is applied to guarantee the required accuracy.

The proposed reference voltage self-calibration algorithm is based on the split capacitor linearity on-chip self-calibration method proposed by Yoshioka et al. [14], which is to correct the output code by comparing the certain capacitors and the rest of all low capacitors. When the certain capacitance is consistent with the rest of all low capacitors, the calibration is finished.

Combining the correlated double sampling circuit technology and the above self-calibration method, the reference voltage self-calibration algorithm is proposed and the flowchart is shown in Figure 13.

The algorithm includes two patterns. Pattern 1 provides the relatively accurate target value when pattern 2 represents the value to be corrected. Two-step scaled reference is used in the process. The reference voltages and are the precise voltages, which generate or by DAC. The or in pattern 2 is the internally generated voltage, which is a rough value and needs to be corrected.

The precise voltages and rough voltages are converted into digital code through ADC. The difference between precise voltages and rough voltages determines the action of counter. Once the difference is equal to zero, the calibration is finished. If the difference is not equal to zero, the counter will add one or minus one and the output of DAC will get closer to the target value.

The capacitor array of calibration pattern is shown in Figure 14 when the capacitor array of calibration pattern is shown in Figure 15. Both work on the same principle, but the output of DAC in the calibration is limited. For a differential ADC, the single-ended voltage can only reach . If the lower plates of capacitors are connected to the +VF/128, the results of ADC will exceed the conversion range, which is not accurate.

Assuming that the error of A/D conversion is 1LSB, the digital code in pattern 1 is equal to 00000010000000 when correcting . If the reference voltage is provided from a relatively small value by pattern 2, the digital code will keep on the 00000010000000, which is not consistent with the real value. However, the is equal to , which means the calibration has finished. During the process, the reference voltage self-calibration algorithm does not take on the job, so the reference voltages should change from a large value and the calibration of is the same as well.

Figure 16 shows the timing block of calibration. PAT_BUS is the bus signal that controls the DAC capacitance switch. When the system is powered on, the signal RESETD resets the digital circuit and then the signal CAL_BEGIN jumps to the high level, which means the calibration module begins to work. The timing of A/D conversion is the same as SAR ADC. A single complete calibration cycle includes 2 settings of switch mode and 2 A/D conversions. Once the second conversion is finished, the signal ADC_DONE will turn to a high level. The compared results of two conversions determine the state of calibration.

If the calibration is over, the signal CAL_OK becomes a high level, which represents the work of one reference voltage calibration has been finished. If the signal CLK_OKs of two references are high level, the whole calibration will be finished and the signal NORMAL will turn to a high level as well.

4. Experimental Results

The CMOS image sensor is fabricated in the 180 nm CMOS process, which is used in remote sensing. Referring to the capacitor array, MIM capacitors are chosen, which have a better match and less affected by temperature compared with others. The pixel array is , and the pixel pitch is . The photography of the chip is shown in Figure 17 and the layout of the chip is shown in Figure 18, which are consistent. The pixel array is put in the center of the chip while the readout circuits are placed on the left and right sides. The whole area of the chip is  mm2, where the pixel array occupies the main area.

When it comes to SAR ADC, the performance contains static performance and dynamic performance. Due to the combination of PGA and SAR ADC, the performance of SAR ADC is affected by PGA and the following presentation includes the effect of PGA. The static performance is shown in Figure 19. The DNL is +1.4/-0.25 LSB and the INL is +1.1/-2.1 LSB, which reflects the transient noise. At the sampling speed of 150 kS/s, the SNR and SFDR of the SAR ADC are 71.72 dB and 82.91 dB, respectively, when the frequency of the input signal is 33.3 kHz, which is shown in Figure 20. What is more, the THD of SAR ADC is -75.79 dB and the SINAD is 70.28 dB. In order to verify the stability performance of the proposed prototype, eight chips are tested to get the data, which is presented in Figure 21. The SNR of SAR ADC is from 68.78 dB to 71.71 dB when the ENOB is from 10.8 bits to 11.3 bits, whose performance is relatively stable. The single SAR ADC consumes 477.2 uW.

Figure 22 shows the photos captured by the proposed CIS chips, in which the edge of the subjects can be clearly recognized. What is more, the depth of the background color can be clearly identified, which means the CIS have a good resolution. The performance summary of the prototype is listed in Table 2, including SAR ADC, PGA, and the CIS. The total power consumption of the CIS is about 613 mW.


ParameterValue

Process180 nm CMOS process
Analog supply3.3 V
Digital supply3.3 V
ADC
 Resolution14 bits
 Sample rate150 kSps
 Input range-2.4 V ~ +2.4 V
 DNL+1.4/-0.25LSB
 INL+1.1/-2.1LSB
 SNR71.7 dB
 SFDR82.91 dB
 SINAD70.28 dB
 Power consumption477.2 uW
PGA
 Gain3x, 4x, 6x
CIS
 Frame rate50 fps
 Pixel number
 Pixel pitch
 Temporal noise13.6 erms
 Total power613 mW

Compared with the previous works, which are depicted in Table 3, this work adopts the large pixel array and the resolution of SAR ADC is comparatively high without the help of complex calibration and the advanced technology. The proposed CIS chip keeps a balance between the area, resolution, and speed.


ParameterThis workJSSC 16 [15]TED 16 [16]ISSCC 18 [17]JSSC 19 [18]

Process (nm)180180909065
ADC typeSARSARSARSARSAR
Supply voltage (V)3.32.8/1.82.8/1.21.8/13.4
Number of pixel
Pixel pitch (μm)12.54.41.121.51.5
Frame rate (fps)501006060170
Resolution (bit)1410121010

5. Conclusions

The 14-bit fully differential SAR ADC with PGA is proposed to apply on CIS. In this paper, the scale of pixel array is large when the three-way PGA is used to sample at the same time to increase the speed. What is more, it also provides three types of gain: 3x, 4x, and 6x. Considering the reset and exposure signal, the fixed deviation is added into the PGA, which makes the input signal distributed evenly on the positive and negative sides. When it comes to SAR ADC, the two-step scaled-reference voltages are adopted to realize the goal of 14-bit A/D conversion with a 7-bit complementary capacitor array, which is aimed at reducing the number and the area of capacitors. In order to make the precision of reference voltage meet the requirement, the reference voltage self-calibration algorithm is used. During the whole process, the offset and matching accuracy needs to be considered as well. By finishing the above design, the readout circuit realizes the function well and the proposed CIS achieves the goal of high resolution for remote sensing, which are verified in the manufactured chips.

Data Availability

The data used to support the findings of this study are available from the corresponding author upon request.

Conflicts of Interest

The authors declare that they have no conflicts of interest.

Acknowledgments

This work was supported by the National Key R&D Program of China (2018YFB0904900 and 2018YFB0904902).

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Copyright © 2021 Xiaowei Zhang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


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