A Compact FPGA-Based Accelerator for Curve-Based Cryptography in Wireless Sensor Networks

Table 1

Hardware approaches for multipliers.

Ref.	Field	Target	Algorithm	Approach	Slices	Time (ns)
[24]		Spartan 3	MSE	Digit-serial	3458	58.0
[24]		Spartan 3	LSE	Digit-serial	3504	62.0
[24]		Spartan 3	MSE	Digit-serial	5406	153.0
[28]		Virtex 6	Schoolbook method	Digit-serial	1643 (LUTs)	802.4
[32] (d =1)		Virtex 5	LSE	Digit-serial	714 (LUTs)	415.0
[32] (d =16)		Virtex 5	LSE	Digit-serial	2351 (LUTs)	35.0
[34]		Spartan 3	MSE	Digit-digit	406	219.0
[33]		Virtex II	M-I algorithm	Systolic array	1399