Table of Contents Author Guidelines Submit a Manuscript
Mobile Information Systems
Volume 2016, Article ID 7048482, 6 pages
Research Article

LDPC Decoding on GPU for Mobile Device

School of Electronic and Information Engineering, South China University of Technology, Tianhe District, Guangzhou, China

Received 17 May 2016; Revised 17 August 2016; Accepted 25 August 2016

Academic Editor: Mariusz Głąbowski

Copyright © 2016 Yiqin Lu et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. R. G. Gallager, “Low-density parity-check codes,” IRE Transactions on Information Theory, vol. 8, no. 1, pp. 21–28, 1962. View at Google Scholar · View at MathSciNet
  2. D. J. C. MacKay and R. M. Neal, “Near Shannon limit performance of low density parity check codes,” Electronics Letters, vol. 32, no. 18, pp. 1645–1646, 1996. View at Publisher · View at Google Scholar · View at Scopus
  3. T. Zhang and K. K. Parhi, “A 54 Mbps (3,6)-regular FPGA LDPC decoder,” in Proceedings of the IEEE Workshop on Signal Processing Systems (SIPS '02), October 2002. View at Publisher · View at Google Scholar
  4. D. Chang, F. Yu, Z. Xiao et al., “FPGA verification of a single QC-LDPC code for 100 Gb/s optical systems without error floor down to BER of 10-15,” in Proceedings of the 2011 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC '11), Los Angeles, Calif, USA, March 2011. View at Scopus
  5. G. Falcão, V. Silva, and L. Sousa, “How GPUs can outperform ASICs for fast LDPC decoding,” in Proceedings of the 23rd International Conference on Supercomputing, Yorktown Heights, NY, USA, June 2009.
  6. G. Falcão, L. Sousa, and V. Silva, “Massive parallel LDPC decoding on GPU,” in Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP '08), pp. 83–90, Salt Lake City, UT, USA, February 2008. View at Publisher · View at Google Scholar
  9. R. J. McEliece, D. J. C. MacKay, and J.-F. Cheng, “Turbo decoding as an instance of Pearl's ‘belief propagation’ algorithm,” IEEE Journal on Selected Areas in Communications, vol. 16, no. 2, pp. 140–152, 1998. View at Publisher · View at Google Scholar · View at Scopus
  10. J. Zhao, F. Zarkeshvari, and A. H. Banihashemi, “On implementation of min-sum algorithm and its modifications for decoding low-density parity-check (LDPC) codes,” IEEE Transactions on Communications, vol. 53, no. 4, pp. 549–554, 2005. View at Publisher · View at Google Scholar · View at Scopus
  11. R. M. Tanner, “A recursive approach to low complexity codes,” IEEE Transactions on Information Theory, vol. 27, no. 5, pp. 533–547, 1981. View at Publisher · View at Google Scholar · View at MathSciNet
  12. S. Lin and D. J. Costello, Error Control Coding, Pearson Education India, 2004.
  13. D. G. Merrill and A. S. Grimshaw, “Revisiting sorting for GPGPU stream architectures,” in Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques (PACT '10), Vienna, Austria, September 2010.
  14. V. W. Lee, C. Kim, J. Chhugani et al., “Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU,” ACM SIGARCH Computer Architecture News, vol. 38, no. 3, 2010. View at Google Scholar
  15. G. Wang, Y. Xiong, J. Yun, and J. R. Cavallaro, “Accelerating computer vision algorithms using OpenCL framework on the mobile GPU—a case study,” in Proceedings of the 38th IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '13), IEEE, Vancouver, Canada, May 2013. View at Publisher · View at Google Scholar · View at Scopus
  17. A. Munshi, The OpenCL Specification, Khronos OpenCL Working Group 1, 2009.