An Efficient VLSI Linear Array for DCT/IDCT Using Subband Decomposition Algorithm

Table 3

Data flow of the proposed fast DCT processor with pipelined linear-array architecture (Add.-cycle: addition-cycle and Mul.-cycle: multiplication-cycle).

Processor	FA	MA	CA
Add.-cycle_1	$y[0]$	—	$C[0]$
Add.-cycle_2	$y[1]$	—	$C[1]$
Add.-cycle_3	$y[2]$	—	—
Mul.-cycle_1	$y[3]$	$y[2]·0.9239\text{,}$$y[2]·(-0.3827)$	—
		$y[3]·0.3827\text{,}$$y[3]·(0.9239)$
Add.-cycle_4	$y[4]$	—	$C[2]\text{,}$$C[3]$
Mul.-cycle_2	$y[5]$	$y[4]·0.9062\text{,}$$y[4]·(-0.1802)\text{,}$$y[4]·(-0.3182)\text{,}$$y[4]·0.2126$	—
Mul.-cycle_3	$y[6]$	$y[5]·0.3754\text{,}$$y[5]·(-0.0746)\text{,}$$y[5]·0.7682\text{,}$$y[5]·0.5133$	—
Mul.-cycle_4	$y[7]$	$y[6]·0.1802\text{,}$$y[6]·0.9062\text{,}$$y[6]·0.2126\text{,}$$y[6]·0.3182$	—
Mul.-cycle_5	—	$y[7]·(-0.0746)\text{,}$$y[7]·(-0.3754)\text{,}$$y[7]·0.5133\text{,}$$y[7]·0.7682$	—
Add.-cycle_5	—		$C[4]\text{,}$$C[5]\text{,}$$C[6]\text{,}$$C[7]$