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Mathematical Problems in Engineering
Volume 2011, Article ID 380345, 12 pages
http://dx.doi.org/10.1155/2011/380345
Research Article

Constructing Dynamic Multiple-Input Multiple-Output Logic Gates

1Information Security Center, Beijing University of Posts and Telecommunications, P.O.Box 145, Beijing 100876, China
2Department of Physics, Beijing Normal University, Beijing 100875, China
3School of Science, Beijing University of Posts and Telecommunications, Beijing 100876, China

Received 22 May 2011; Revised 9 August 2011; Accepted 16 August 2011

Academic Editor: Kwok W. Wong

Copyright © 2011 Haipeng Peng et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. T. C. Bartee, Computer Architecture and Logic Design, McGraw-Hill, New York, NY, USA, 1991.
  2. M. M. Mano, Computer System Architecture, Prentice-Hall, Englewood Cliffs, NJ, USA, 3rd edition, 1993.
  3. D. Tabak, “Dynamic architecture and LSI modular computer systems,” IEEE Micro, vol. 4, no. 2, pp. 48–66, 1984. View at Google Scholar
  4. G. Taubes, “Computer design meets Darwin,” Science, vol. 277, no. 5334, pp. 1931–1932, 1997. View at Publisher · View at Google Scholar
  5. J. R. Heath, P. J. Kuekes, G. S. Snider, and R. S. Williams, “A defect-tolerant computer architecture: opportunities for nanotechnology,” Science, vol. 280, no. 5370, pp. 1716–1721, 1998. View at Publisher · View at Google Scholar
  6. C. P. Collier, E. W. Wong, M. Belohradský et al., “Electronically configurable molecular-based logic gates,” Science, vol. 285, no. 5426, pp. 391–394, 1999. View at Publisher · View at Google Scholar
  7. S. Lange and M. Middendorf, “Multi-level reconfigurable architectures in the switch model,” Journal of Systems Architecture, vol. 56, no. 2-3, pp. 103–115, 2010. View at Publisher · View at Google Scholar
  8. S. Sinha and W. L. Ditto, “Dynamics based computation,” Physical Review Letters, vol. 81, no. 10, pp. 2156–2159, 1998. View at Google Scholar
  9. K. Chlouverakis and M. J. Adams, “Optoelectronic realization of NOR logic gate using chaotic two-section lasers,” Electronics Letters, vol. 41, no. 6, pp. 359–360, 2005. View at Publisher · View at Google Scholar
  10. D. Kuo, “Chaos and its computing paradigm,” IEEE Potentials, vol. 24, no. 2, pp. 13–15, 2005. View at Publisher · View at Google Scholar
  11. D. Graham-Rowe, “Logic from chaos: new chips use chaos to produce potentially faster, more robust computing,” Technology Review, Massachusetts Institute of Technology, Cambridge, Mass, USA, 2006, http://www.technologyreview.com/business/16989/. View at Google Scholar
  12. T. Munakata, S. Sinha, and W. L. Ditto, “Chaos computing: implementation of fundamental logical gates by chaotic elements,” IEEE Transactions on Circuits and Systems. I: Fundamental Theory and Applications, vol. 49, no. 11, pp. 1629–1633, 2002. View at Publisher · View at Google Scholar
  13. K. Murali, S. Sinha, W. L. Ditto, and A. R. Bulsara, “Reliable logic circuit elements that exploit nonlinearity in the presence of a noise floor,” Physical Review Letters, vol. 102, no. 10, p. 104101, 2009. View at Google Scholar
  14. H. Peng, Y. Yang, L. Li, and H. Luo, “Harnessing piecewise-linear systems to construct dynamic logic architecture,” Chaos, vol. 18, no. 3, article 033107, 2008. View at Publisher · View at Google Scholar
  15. H. Peng, F. Liu, L. Li, Y. Yang, and X. Wang, “Dynamic logic architecture based on piecewise-linear systems,” Physics Letters A, vol. 374, no. 13-14, pp. 1450–1456, 2010. View at Publisher · View at Google Scholar
  16. W. L. Ditto, K. Murali, and S. Sinha, “Exploiting the controlled responses of chaotic elements to design configurable hardware,” Philosophical Transactions of the Royal Society A, vol. 364, no. 1846, pp. 2483–2494, 2006. View at Publisher · View at Google Scholar
  17. D. Normile, “Artificial life gets real as scientists meet in Japan,” Science, vol. 272, no. 5270, pp. 1872–1873, 1996. View at Publisher · View at Google Scholar
  18. M. R. Jahed-Motlagh, B. Kia, W. L. Ditto, and S. Sinha, “Fault tolerance and detection in chaotic computers,” International Journal of Bifurcation and Chaos in Applied Sciences and Engineering, vol. 17, no. 6, pp. 1955–1968, 2007. View at Publisher · View at Google Scholar · View at Zentralblatt MATH
  19. M. Edwards and P. Green, “Run-time support for dynamically reconfigurable computing systems,” Journal of Systems Architecture, vol. 49, no. 4–6, pp. 267–281, 2003. View at Publisher · View at Google Scholar
  20. P. M. Frank, “Analytical and qualitative model-based fault diagnosis—a survey and some new results,” European Journal of Control, vol. 2, no. 1, pp. 6–28, 1996. View at Google Scholar
  21. K. Murali and S. Sinha, “Using synchronization to obtain dynamic logic gates,” Physical Review E, vol. 75, no. 2, Article ID 025201(R), 2007. View at Publisher · View at Google Scholar
  22. K. Murali, A. Miliotis, W. L. Ditto, and S. Sinha, “Logic from nonlinear dynamical evolution,” Physics Letters A, vol. 373, no. 15, pp. 1346–1351, 2009. View at Publisher · View at Google Scholar