Constructing Dynamic Multiple-Input Multiple-Output Logic Gates

Table 3

Logical gates for different values of parameters 𝛽, 𝑘.

Region	𝛽	𝑘	Gate
	(0,1/4]	(−1/2,−𝛽)	0
		(−𝛽,𝛽)	NOR
		(𝛽,1/2−𝛽)	0
		(1/2−𝛽,1/2+𝛽)	𝑋5
(I)		(1/2+𝛽,1−𝛽)	0
		(1−𝛽,1+𝛽)	𝑋6
		(1+𝛽,3/2−𝛽)	0
		(3/2−𝛽,3/2+𝛽)	AND
		(3/2+𝛽,2)	0
	(1/4,1/2]	(−1/2,−𝛽)	0
		(−𝛽,1/2−𝛽)	NOR
		(1/2−𝛽,𝛽)	𝑋7
		(𝛽,1−𝛽)	𝑋5
(II)		(1−𝛽,1/2+𝛽)	XOR
		(1/2+𝛽,3/2−𝛽)	𝑋6
		(3/2−𝛽,1+𝛽)	𝑋8
		(1+𝛽,3/2+𝛽)	AND
		(3/2+𝛽,2)	0
	(1/2,3/4]	(−1/2,1/2−𝛽)	NOR
		(1/2−𝛽,1−𝛽)	𝑋7
		(1−𝛽,𝛽)	NAND
(III)		(𝛽,3/2−𝛽)	XOR
		(3/2−𝛽,1/2+𝛽)	OR
		(1/2+𝛽,1+𝛽)	𝑋8
		(1+𝛽,2)	AND
	(3/4,1]	(−1/2,1/2−𝛽)	NOR
		(1/2−𝛽,1−𝛽)	𝑋7
		(1−𝛽,3/2−𝛽)	NAND
(IV)		(3/2−𝛽,𝛽)	1
		(𝛽,1/2+𝛽)	OR
		(1/2+𝛽,1+𝛽)	𝑋8
		(1+𝛽,2)	AND
	(1,3/2]	(−1/2,1−𝛽)	𝑋7
		(1−𝛽,3/2−𝛽)	NAND
(V)		(3/2−𝛽,𝛽)	1
		(𝛽,1/2+𝛽)	OR
		(1/2+𝛽,2)	𝑋8
	(3/2,2]	(−1/2,3/2−𝛽)	NAND
(VI)		(3/2−𝛽,𝛽)	1
		(𝛽,2)	OR